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Motorola MC68020 User Manual
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MOTOROLA
M68020 USER’S MANUAL
5-
3
5
WORD WRITE
S0
S2
S4
S0
S2
S4
CLK
A31-A2
A1
A0
FC2–FC0
SIZ1
SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31–D24
D23–D16
BYTE WRITE
D15–D8
D7–D0
S0
S2
S4
OP2
OP3
OP3
OP3
WORD
OP3
OP3
OP3
OP3
BYTE
OP2
OP3
OP3
OP3
BYTE WRITE
**
**
**
*
*
For the MC68EC020, A23–A2.
This signal does not apply to the MC68EC020.
Figure
5-26. Byte and Word Write Cycles—32-Bit Port
82
84
Table of Contents
Default Chapter
2
Introduction
2
Table of Contents
3
SECTION 1: OVERVIEW um Rev
16
Features
19
MC68020/EC020 Block Diagram
20
Programming Model
21
Supervisor Programming Model Supplement
23
Status Register (SR)
24
Data Types and Addressing Modes Overview
25
Instruction Set Overview
27
Virtual Memory and Virtual Machine Concepts
27
Virtual Memory
27
Virtual Machine
29
Pipelined Architecture
29
Cache Memory
30
Processing States
31
Privilege Levels
32
Supervisor Privilege Level
32
User Privilege Level
33
Changing Privilege Level
33
Address Space Types
34
Exception Processing
35
Exception Vectors
35
Exception Stack Frame
36
Signal Description
37
Functional Signal Groups
37
Signal Index
38
Function Code Signals (FC2-FC0)
38
Address Bus (A31-A0, MC68020)(A23-A0, MC68EC020)
38
Data Bus (D31-D0)
38
Transfer Size Signals (SIZ1, SIZ0)
38
Signal Index
39
Asynchronous Bus Control Signals
40
Interrupt Control Signals
41
Bus Arbitration Control Signals
42
Bus Exception Control Signals
42
Emulator Support Signal
43
Clock (CLK)
43
Power Supply Connections
43
Signal Summary
44
On-Chip Cache Memory
45
On-Chip Cache Organization and Operation
45
MC68020/EC020 On-Chip Cache Organization
46
Cache Reset
47
Cache Control
47
Cache Control Register (CACR)
47
Cache Address Register (CAAR)
48
Bus Operation
49
Bus Transfer Signals
49
Bus Control Signals
50
Address Bus
51
Address Strobe
51
Data Bus
51
Data Strobe
52
Data Buffer Enable
52
Bus Cycle Termination Signals
52
Data Transfer Mechanism
53
Dynamic Bus Sizing
53
Internal Operand Representation
54
SIZ1, SIZ0 Signal Encoding
55
Data Bus Requirements for Read Cycles
56
Long-Word Operand Write to Word Port Example
58
Long-Word Operand Write to Word Port Timing
59
Word Operand Write to Byte Port Example
60
Word Operand Write to Byte Port Timing
61
Misaligned Operands
62
Misaligned Long-Word Operand Write to Word Port Timing
63
Misaligned Word Operand Write to Word Port Example
64
Misaligned Word Operand Write to Word Port Timing
65
Misaligned Word Operand Read from Word Bus Example
66
Effects of Dynamic Bus Sizing and Operand Misalignment
68
Address, Size, and Data Bus Relationships
69
Cache Interactions
70
Byte Enable Signal Generation for 16- and 32-Bit Ports
71
Bus Operation
72
Data Transfer Cycles
73
Read Cycle
74
Byte Read Cycle Flowchart
75
Byte and Word Read Cycles—32-Bit Port
76
Long-Word Read—8-Bit Port
77
Long-Word Read—16- and 32-Bit Ports
78
Write Cycle
81
Read-Write-Read Cycles—32-Bit Port
82
Byte and Word Write Cycles—32-Bit Port
83
Long-Word Operand Write—8-Bit Port
84
Long-Word Operand Write—16-Bit Port
85
Read-Modify-Write Cycle
87
Read-Modify-Write Cycle Flowchart
88
Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction)
89
CPU Space Cycles
92
Interrupt Acknowledge Bus Cycles
93
Interrupt Acknowledge Cycle-Terminated Normally
93
Interrupt Acknowledge Cycle Flowchart
94
Interrupt Acknowledge Cycle Timing
95
Autovector Interrupt Acknowledge Cycle
96
Spurious Interrupt Cycle
96
Autovector Operation Timing
97
Breakpoint Acknowledge Cycle
98
Breakpoint Acknowledge Cycle Timing
99
Breakpoint Acknowledge Cycle Timing (Exception Signaled)
100
Coprocessor Communication Cycles
101
Bus Exception Control Cycles
101
Bus Errors
103
Retry Operation
104
Late Retry
107
Halt Operation
108
Double Bus Fault
108
Halt Operation Timing
109
Bus Synchronization
110
Bus Arbitration
110
MC68020 Bus Arbitration
111
MC68020 Bus Arbitration Flowchart for Single Request
112
MC68020 Bus Arbitration Operation Timing for Single Request
113
Bus Request (MC68020)
114
Bus Grant (MC68020)
114
Bus Grant Acknowledge (MC68020)
114
Bus Arbitration Control (MC68020)
115
MC68020 Bus Arbitration Operation Timing—Bus Inactive
117
MC68EC020 Bus Arbitration
118
Bus Request (MC68EC020)
119
Bus Grant (MC68EC020)
119
MC68EC020 Bus Arbitration Operation Timing for Single Request
120
Bus Arbitration Control (MC68EC020)
121
MC68EC020 Bus Arbitration Operation Timing—Bus Inactive
123
Reset Operation
124
Initial Reset Operation Timing
125
RESET Instruction Timing
126
Exception Processing
127
Exception Processing Sequence
127
Exception Vector Assignments
129
Reset Exception
130
Bus Error Exception
130
Reset Operation Flowchart
131
Address Error Exception
132
Instruction Trap Exception
132
Illegal Instruction and Unimplemented Instruction Exceptions
133
Privilege Violation Exception
134
Trace Exception
135
Format Error Exception
136
Interrupt Exceptions
137
Interrupt Pending Procedure
138
Interrupt Recognition Examples
140
Assertion of IPEND (MC68020 Only)
141
Interrupt Exception Processing Flowchart
142
Breakpoint Instruction Exception
144
Multiple Exceptions
144
Breakpoint Instruction Flowchart
145
Return from Exception
146
RTE Instruction for Throwaway Four-Word Frame
147
Bus Fault Recovery
148
Special Status Word (SSW)
148
Special Status Word Format
149
Using Software to Complete the Bus Cycles
150
Completing the Bus Cycles with RTE
151
Coprocessor Considerations
152
Exception Stack Frame Formats
152
Coprocessor Interface Description
155
Introduction
155
Interface Features
156
Concurrent Operation Support
156
Coprocessor Instruction Format
157
Coprocessor System Interface
158
Coprocessor Classification
158
Coprocessor Interface Register Selection
159
Processor-Coprocessor Interface
159
Coprocessor Instruction Types
161
Coprocessor General Instructions
162
Branch on Coprocessor Condition Instruction
166
Set on Coprocessor Condition Instruction
168
Format
170
Protocol
170
Protocol
171
Coprocessor Context Save and Restore Instructions
171
Coprocessor Internal State Frames
172
Coprocessor Format Words
173
Empty/Reset Format Word
173
Not-Ready Format Word
174
Valid Format Word
175
Coprocessor Context Restore Instruction
177
Coprocessor Interface Register Set
179
Response CIR
179
Control CIR
179
Save CIR
180
Restore CIR
180
Operation Word CIR
180
Command CIR
180
Condition CIR
181
Operand CIR
181
Register Select CIR
182
Instruction Address CIR
182
Operand Address CIR
182
Coprocessor Response Primitives
182
Scanpc
183
Coprocessor Response Primitive General Format
183
Busy Primitive
185
Null Primitive
186
Null Coprocessor Response Primitive Encodings
187
Supervisor Check Primitive
188
Transfer Operation Word Primitive
188
Transfer from Instruction Stream Primitive
189
Evaluate and Transfer Effective Address Primitive
190
Evaluate Effective Address and Transfer Data Primitive
190
Valid Effective Address Field Codes
191
Write to Previously Evaluated Effective Address Primitive
192
Take Address and Transfer Data Primitive
194
Transfer To/From Top of Stack Primitive
195
Transfer Single Main Processor Register Primitive
195
Transfer Main Processor Control Register Primitive
196
Transfer Multiple Main Processor Registers Primitive
197
Transfer Multiple Coprocessor Registers Primitive
197
Transfer Multiple Coprocessor Registers Primitive Format
198
Transfer Status Register and Scanpc Primitive
199
Take Preinstruction Exception Primitive
200
MC68020/EC020 Preinstruction Stack Frame
201
Take Midinstruction Exception Primitive
202
Take Postinstruction Exception Primitive
203
Coprocessor-Detected Exceptions
204
Coprocessor-Detected Protocol Violations
205
Coprocessor-Detected Illegal Command or Condition Words
206
Coprocessor Data-Processing-Related Exceptions
206
Coprocessor System-Related Exceptions
206
Format Errors
207
Main-Processor-Detected Exceptions
207
Protocol Violations
207
Exceptions Related to Primitive Processing
208
F-Line Emulator Exceptions
209
Privilege Violations
210
Cptrapcc Instruction Traps
210
Trace Exceptions
210
Interrupts
211
Format Errors
212
Address and Bus Errors
212
Coprocessor Reset
213
Coprocessor Summary
213
Instruction Execution Timing
216
Timing Estimation Factors
216
Instruction Cache and Prefetch
216
Operand Misalignment
217
Bus/Sequencer Concurrency
217
Instruction Execution Overlap
218
Instruction Stream Timing Examples
219
Processor Activity for Example 1
220
Processor Activity for Example 2
221
Processor Activity for Example 3
222
Processor Activity for Example 4
223
Instruction Timing Tables
224
Instruction Timings from Timing Tables
226
Fetch Effective Address
228
Fetch Immediate Effective Address
229
Calculate Effective Address
231
Calculate Immediate Effective Address
232
Jump Effective Address
234
MOVE Instruction
235
Special-Purpose MOVE Instruction
244
Arithmetic/Logical Instructions
245
Immediate Arithmetic/Logical Instructions
246
Binary-Coded Decimal Operations
247
Single-Operand Instructions
248
Shift/Rotate Instructions
249
Bit Manipulation Instructions
250
Bit Field Manipulation Instructions
251
Conditional Branch Instructions
252
Control Instructions
253
Exception-Related Instructions
254
Save and Restore Operations
255
Applications Information
256
Floating-Point Units
256
Bit Data Bus Coprocessor Connection
257
Chip Select Generation PAL
258
Chip Select PAL Equations
259
Byte Select Logic for the MC68020/EC020
260
Data Bus Activity for Byte, Word, and Long-Word Ports
261
Example MC68020/EC020 Byte Select PAL System Configuration
262
MC68020/EC020 Byte Select PAL Equations
263
Power and Ground Considerations
264
Clock Driver
265
Memory Interface
266
Access Time Calculations
267
Access Time Computation Diagram
268
Memory Access Time Equations at 16.67 and 25 Mhz
269
Module Support
270
Module Descriptor
270
Module Stack Frame
272
Access Levels
273
Access Level Control Bus Registers
273
Module Call
274
Module Return
275
Electrical Characteristics
276
Maximum Ratings
276
Thermal Considerations
276
MC68020 Thermal Characteristics and DC Electrical Characteristics
277
MC68EC020 Thermal Characteristics and DC Electrical Characteristics
279
AC Electrical Characteristics
280
Drive Levels and Test Points for AC Specifications
281
Clock Input Timing Diagram
282
Read Cycle Timing Diagram
286
Write Cycle Timing Diagram
287
Bus Arbitration Timing Diagram
288
Ordering Information and Mechanical Data
289
Standard Ordering Information
289
Standard MC68020 Ordering Information
289
Standard MC68EC020 Ordering Information
289
Pin Assignments and Package Dimensions
290
MC68020 RC and RP Suffix-Pin Assignment
290
MC68020 RC Suffix-Package Dimensions
291
MC68020 RP Suffix-Package Dimensions
292
MC68020 FC and FE Suffix-Pin Assignment
293
MC68020 FC Suffix-Package Dimensions
294
MC68020 FE Suffix-Package Dimensions
295
MC68EC020 RP Suffix-Pin Assignment
296
MC68EC020 RP Suffix-Package Dimensions
297
MC68EC020 FG Suffix-Pin Assignment
298
MC68EC020 FG Suffix-Package Dimensions
299
Appendix A
300
Interfacing an MC68EC020 to a DMA Device that
300
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Motorola MC68020 Specifications
General
Brand
Motorola
Model
MC68020
Category
Computer Hardware
Language
English
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