MOTOROLA M68020 USER’S MANUAL 8- 31
8.2.9 Immediate Arithmetic/Logical Instructions
The immediate arithmetic/logical instructions table indicates the number of clock periods
needed for the processor to fetch the source immediate data value and perform the
specified arithmetic/logical operation using the specified destination addressing mode.
Footnotes indicate when to add appropriate fetch effective or fetch immediate effective
address time. This computation will give the total execution time needed to perform the
appropriate immediate arithmetic/logical operation. The total number of clock cycles is
outside the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction Best Case Cache Case Worst Case
MOVEQ #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
ADDQ #<data>,Rn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* ADDQ #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
SUBQ #<data>,Rn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* SUBQ #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** ADDI #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
** ADDI #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** ANDI #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
** ANDI #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** EORI #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
** EORI #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** ORI #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
** ORI #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** SUBI #<data>,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
** SUBI #<data>,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
** CMPI #<data>,EA 0(0/0/0) 2(0/0/0) 3(0/1/0)
*Add Fetch Effective Address Time
** Add Fetch Immediate Address Time
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