8- 10 M68020 USER’S MANUAL MOTOROLA
entry is 17 (2/0/0). For the best case, there are no instruction accesses because the cache
is enabled and the sequencer does not have to go to external memory for the instruction
words.
The first tables deal exclusively with fetching and calculating effective addresses and
immediate operands. The tables are arranged in this manner because some instructions
do not require effective address calculation or fetching. For example, the instruction CLR
<ea> (found in the table under 8.2.11 Single Operand Instructions) only needs to have a
calculated effective address time added to its table entry because no fetch of an operand
is required. This instruction only writes to memory or a register. Some instructions use
specific addressing modes which exclude timing for calculation or fetching of an operand.
When these instances arise, they are footnoted to indicate which other tables are needed
in the timing calculation.
Many two-word instructions (e.g., MULU.L, DIV.L, BFSET, etc.) include the fetch
immediate effective address time or the calculate immediate effective address time in the
execution time calculation. The timing for immediate data of word length (#<data>.W) is
used for these calculations. If the instruction has a source and a destination, the source
effective address is used for the table lookup. If the instruction is single operand, the
effective address of that operand is used.
The following example includes multiword instructions that refer to the fetch immediate
effective address and calculate immediate effective address tables in 8.2 Instruction
Timing Tables.
Instruction
#1) MULU.L D7,D1:D2
#2) BFCLR $6000{0:8}
#3) DIVS.L #$10000,D3:D4
CC
1.MULU.L (D7),D1:D2
#<data>.W,Dn 2
MUL.L EA,Dn 43
2.BFCLR $6000{0:8}
#<data>.W.,$XXX.W 5
BFCLR Mem (<5 bytes) 16
3.DIVS.L #$10000,D3:D4
#<data>.W,#<data>.L 6
DIVS.L EA, Dn 90
Execution time = 2 + 43 + 5 + 16 + 6 + 90
= 102 clock periods
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