MOTOROLA M68020 USER’S MANUAL 1- 1
SECTION 1
INTRODUCTION
The MC68020 is the first full 32-bit implementation of the M68000 family of
microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented
with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile
addressing modes.
The MC68020 is object-code compatible with earlier members of the M68000 family and
has the added features of new addressing modes in support of high-level languages, an
on-chip instruction cache, and a flexible coprocessor interface with full IEEE floating-point
support (the MC68881 and MC68882). The internal operations of this microprocessor
operate in parallel, allowing multiple instructions to be executed concurrently.
The asynchronous bus structure of the MC68020 uses a nonmultiplexed bus with 32 bits
of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism
that allows the processor to transfer operands to or from external devices while
automatically determining device port size on a cycle-by-cycle basis. The dynamic bus
interface allows access to devices of differing data bus widths, in addition to eliminating all
data alignment restrictions.
The MC68EC020 is an economical high-performance embedded microprocessor based
on the MC68020 and has been designed specifically to suit the needs of the embedded
microprocessor market. The major differences in the MC68EC020 and the MC68020 are
that the MC68EC020 has a 24-bit address bus and does not implement the following
signals:
ECS, OCS, DBEN, IPEND, and BGACK. Also, the available packages and
frequencies differ for the MC68020 and MC68EC020 (see Section 11 Ordering
Information and Mechanical Data.) Unless otherwise stated, information in this manual
applies to both the MC68020 and the MC68EC020.
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