Motorola MC68030 User Manual

Bus Operation
7-101 MC68030 USER’S MANUAL MOTOROLA
7.7.2 Bus Grant
The processor asserts BG as soon as possible after receipt of BR. This is immediately
following internal synchronization except during a read-modify-write cycle or following an
internal decision to execute a bus cycle. During a read-modify-write cycle, the processor
does not assert BG
until the entire operation has completed. RMC is asserted to indicate
Figure 7-60. Bus Arbitration Operation Timing
A31-A0
FC2-FC0
ECS
OCS
AS
DS
DSACK1
CLK
S0 S4 S0
SIZ1-SIZ0
R/W
DSACK0
DBEN
S2 S2
BGACK
BG
BR
D31-D0
CONTROLLER DMA DEVICE CONTROLLER

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English