Bus Operation
7-2
MC68030 USER’S MANUAL
MOTOROLA
The bus can operate in an asynchronous mode identical to the MC68020 bus for any port
width. The bus and control input signals used for asynchronous operation are internally
synchronized to the MC68030 clock, introducing a delay. This delay is the time period
required for the MC68030 to sample an asynchronous input signal, synchronize the input to
the internal clocks of the processor, and determine whether it is high or low. Figure 7-1
shows the relationship between the clock signal and the associated internal signal of a
typical asynchronous input.
Furthermore, for all asynchronous inputs, the processor latches the level of the input during
a sample window around the falling edge of the clock signal. This window is illustrated in
Figure 7-2. To ensure that an input signal is recognized on a specific falling edge of the
clock, that input must be stable during the sample window. If an input makes a transition
during the window time period, the level recognized by the processor is not predictable;
however, the processor always resolves the latched level to either a logic high or low before
using it. In addition to meeting input setup and hold times for deterministic operation, all input
signals must obey the protocols described in this section.
Figure 7-1. Relationship between External and Internal Signals
SYNC DELAY
CLK
EXT
INT
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