Bus Operation
7-12
MC68030 USER’S MANUAL
MOTOROLA
Figure 7-7 shows a word transfer to an 8-bit bus port. Like the preceding example, this
example requires two bus cycles. Each bus cycle transfers a single byte. The size signals
for the first cycle specify two bytes; for the second cycle, one byte. Figure 7-8 shows the
associated bus transfer signal timing.
Figure 7-6. Long-Word Operand Write Timing (16-Bit Data Port)
WORD WRITE
LONG WORD OPERAND WRITE TO 16-BIT PORT
S0 S2 S4 S0 S2 S4
CLK
A31-A2
A1
A0
FC2-FC0
SIZ1
SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
WORD WRITE
OP0
OP1
OP2
OP3
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