Bus Operation
MOTOROLA
MC68030 USER’S MANUAL
7-15
Figure 7-9 shows the transfer of a long-word operand to an odd address in word-organized
memory, which requires three bus cycles. For the first cycle, the size signals specify a long-
word transfer, and the address offset (A2:A0) is 001. Since the port width is 16 bits, only the
first byte of the long word is transferred. The slave device latches the byte and
acknowledges the data transfer, indicating that the port is 16 bits wide. When the processor
starts the second cycle, the size signals specify that three bytes remain to be transferred
with an address offset (A2:A0) of 010. The next two bytes are transferred during this cycle.
The processor then initiates the third cycle, with the size signals indicating one byte
remaining to be transferred. The address offset (A2:A0) is now 100; the port latches the final
byte; and the operation is complete. Figure 7-10 shows the associated bus transfer signal
timing.
Figure 7-11 shows the equivalent operation for a cachable data read cycle.
Figures 7-12 and 7-13 show a word transfer to an odd address in word-organized memory.
This example is similar to the one shown in Figures 7-9 and 7-10 except that the operand is
word sized and the transfer requires only two bus cycles.
Figure 7-14 shows the equivalent operation for a cachable data read cycle.
Figure 7-9. Misaligned Long-Word Transfer to Word Port Example
DATA BUS
D31 D16
LONG WORD OPERAND
OP0 OP1 OP2 OP3
31 0
WORD MEMORY
MSB
LSB
XXX OP0
OP1 OP2
MC68EC030
SIZ1 SIZ0 A1
A0
0000
1101
MEMORY CONTROL
DSACK1 DSACK0
LH
LH
XXXOP3
LH
A0
1
0
01100
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