MOTOROLA
MC68030 USER’S MANUAL
xxxix
Figure
Number
Title
Page
Number
LIST OF ILLUSTRATIONS (Continued)
7-35 Synchronous Read-Modify-Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . 7-55
7-36 Synchronous Read-Modify-Write Cycle Timing — CIIN
Asserted . . . . . . . 7-56
7-37 Burst Operation Flowchart — Four Long Words Transferred. . . . . . . . . . . 7-62
7-38 Long-Word Operand Request from $07 with
Burst Request and Wait Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-63
7-39 Long-Word Operand Request from $07 with
Burst Request — CBACK
Negated Early. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
7-40 Long-Word Operand Request from $0E — Burst Fill Deferred . . . . . . . . . 7-65
7-41 Long-Word Operand Request from $07 with
Burst Request — CBACK
and CIIN Asserted . . . . . . . . . . . . . . . . . . . . . . 7-66
7-42 MC68030 CPU Space Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . 7-69
7-43 Interrupt Acknowledge Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-71
7-44 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72
7-45 Autovector Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
7-46 Breakpoint Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-75
7-47 Breakpoint Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-76
7-48 Breakpoint Acknowledge Cycle Timing (Exception Signaled) . . . . . . . . . . 7-77
7-49 Bus Error without DSACKx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-84
7-50 Late Bus Error with DSACKx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-85
7-51 Late Bus Error with STERM
— Exception Taken. . . . . . . . . . . . . . . . . . . . 7-86
7-52 Long-Word Operand Request — Late BERR
on Third Access . . . . . . . . . 7-87
7-53 Long-Word Operand Request — BERR
on Second Access . . . . . . . . . . . 7-88
7-54 Asynchronous Late Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-90
7-55 Synchronous Late Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91
7-56 Late Retry Operation for a Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-92
7-57 Halt Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
7-58 Bus Synchronization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-96
7-59 Bus Arbitration Flowchart for Single Request. . . . . . . . . . . . . . . . . . . . . . . 7-98
7-60 Bus Arbitration Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
7-61 Bus Arbitration State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-101
7-62 Single-Wire Bus Arbitration Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 7-103
7-63 Bus Arbitration Operation (Bus Inactive) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-104
7-64 Initial Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-105
7-65 Processor-Generated Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-106
8-1 Reset Operation Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8-2 Interrupt Pending Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8-3 Interrupt Recognition Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8-4 Assertion of IPEND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8-5 Interrupt Exception Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8-6 Examples of Interrupt Recognition and Instruction Boundaries . . . . . . . . . 8-20
8-7 Breakpoint Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
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