Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-37
State 1
One-half clock later in state 1 (S1), the processor asserts AS
indicating that the address
on the address bus is valid. The processor also asserts DS
also during S1. In addition,
the ECS
(and OCS, if asserted) signal is negated during S1.
State 2
During state 2 (S2), the processor asserts DBEN to enable external data buffers. The
selected device uses R/W
, SIZ0–SIZ1, A0–A1, CIOUT, and DS to place its information on
the data bus, and drives CIIN if appropriate. Any or all of the bytes (D24–D31, D16–D23,
D8–D15, and D0–D7) are selected by SIZ0–SIZ1 and A0–A1. Concurrently, the selected
device asserts DSACKx
.
State 3
As long as at least one of the DSACKx
signals is recognized by the end of S2 (meeting
the asynchronous input setup time requirement), data is latched on the next falling edge
of the clock, and the cycle terminates. If DSACKx
is not recognized by the start of state 3
(S3), the processor inserts wait states instead of proceeding to states 4 and 5. To ensure
that wait states are inserted, both DSACK0
and DSACK1 must remain negated
throughout the asynchronous input setup and hold times around the end of S2. If wait
states are added, the processor continues to sample the DSACKx
signals on the falling
edges of the clock until one is recognized.
State 4
The processor samples CIIN
at the beginning of state 4 (S4). Since CIIN is defined as a
synchronous input, whether asserted or negated, it must meet the appropriate
synchronous input setup and hold times on every rising edge of the clock while AS
is
asserted. At the end of S4, the processor latches the incoming data.
State 5
The processor negates AS
, DS, and DBEN during state 5 (S5). It holds the address valid
during S5 to provide address hold time for memory systems. R/W
, SIZ0–SIZ1, and FC0–
FC2 also remain valid throughout S5.
The external device keeps its data and DSACK
x signals asserted until it detects the
negation of AS
or DS (whichever it detects first). The device must remove its data and
negate DSACKx
within approximately one clock period after sensing the negation of AS
or DS. DSACKx signals that remain asserted beyond this limit may be prematurely
detected for the next bus cycle.
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