Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-49
State 6
The processor asserts ECS
and OCS in S6 to indicate that another external cycle is
beginning. The processor drives R/W
low for a write cycle. CIOUT also becomes valid,
indicating the state of the MMU CI bit in the address translation descriptor or in a relevant
TTx register. Depending on the write operation to be performed, the address lines may
change during S6.
State 7
In S7, the processor asserts AS
, indicating that the address on the address bus is valid.
The processor also asserts DBEN
, which can be used to enable data buffers during S7.
In addition, the ECS
(and OCS, if asserted) signal is negated during S7.
State 8
During S8, the processor places the data to be written onto D0–D31.
State 9
The processor asserts DS
during S9 indicating that the data is stable on the data bus. As
long as at least one of the DSACK
x signals is recognized by the end of S8 (meeting the
asynchronous input setup time requirement), the cycle terminates one clock later. If
DSACK
x is not recognized by the start of S9, the processor inserts wait states instead of
proceeding to S10 and S11. To ensure that wait states are inserted, both DSACK0
and
DSACK1
must remain negated throughout the asynchronous input setup and hold times
around the end of S8. If wait states are added, the processor continues to sample
DSACK
x signals on the falling edges of the clock until one is recognized.
The selected device uses R/W
, DS, SIZ0–SIZ1, and A0–A1 to latch data from the
appropriate section(s) of the data bus (D24–D31, D16–D23, D8–D15, and D0–D7).
SIZ0–SIZ1 and A0–A1 select the data bus sections. If it has not already done so, the
device asserts DSACK
x when it has successfully stored the data.
State 10
The processor issues no new control signals during S10.
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