MOTOROLA
MC68030 USER’S MANUAL
xli
Figure
Number
Title
Page
Number
LIST OF ILLUSTRATIONS (Continued)
9-38 MMU Status Register (MMUSR) Format . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59
9-39 MMU Status Interpretation PTEST Level 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-62
9-40 MMU Status Interpretation PTEST Level 7 . . . . . . . . . . . . . . . . . . . . . . . . 9-63
10-1 F-Line Coprocessor Instruction Operation Word . . . . . . . . . . . . . . . . . . . . 10-4
10-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage. . 10-6
10-3 MC68030 CPU Space Address Encodings . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10-4 Coprocessor Address Map in MC68030 CPU Space. . . . . . . . . . . . . . . . . 10-8
10-5 Coprocessor Interface Register Set Map . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10-6 Coprocessor General Instruction Format (cpGEN) . . . . . . . . . . . . . . . . . . 10-10
10-7 Coprocessor Interface Protocol for General Category Instructions . . . . . . 10-11
10-8 Coprocessor Interface Protocol for Conditional Category Instructions. . . . 10-13
10-9 Branch on Coprocessor Condition Instruction (cpBcc.W) . . . . . . . . . . . . . 10-14
10-10 Branch On Coprocessor Condition Instruction (cpBcc.L). . . . . . . . . . . . . . 10-14
10-11 Set On Coprocessor Condition (cpScc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10-12 Test Coprocessor Condition, Decrement and Branch
Instruction Format (cpDBcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10-13 Trap On Coprocessor Condition (cpTRAPcc) . . . . . . . . . . . . . . . . . . . . . . 10-18
10-14 Coprocessor State Frame Format in Memory . . . . . . . . . . . . . . . . . . . . . . 10-21
10-15 Coprocessor Context Save Instruction Format (cpSAVE) . . . . . . . . . . . . . 10-25
10-16 Coprocessor Context Save Instruction Protocol. . . . . . . . . . . . . . . . . . . . . 10-26
10-17 Coprocessor Context Restore Instruction Format (cpRESTORE) . . . . . . . 10-27
10-18 Coprocessor Context Restore Instruction Protocol . . . . . . . . . . . . . . . . . . 10-28
10-19 Control CIR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10-20 Condition CIR Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10-21 Operand Alignment for Operand CIR Accesses. . . . . . . . . . . . . . . . . . . . . 10-32
10-22 Coprocessor Response Primitive Format. . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10-23 Busy Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10-24 Null Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
10-25 Supervisor Check Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10-26 Transfer Operation Word Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . 10-41
10-27 Transfer from Instruction Stream Primitive Format . . . . . . . . . . . . . . . . . . 10-41
10-28 Evaluate and Transfer Effective Address Primitive Format . . . . . . . . . . . . 10-42
10-29 Evaluate Effective Address and Transfer Data Primitive . . . . . . . . . . . . . . 10-43
10-30 Write to Previously Evaluated EffectiveAddress Primitive Format . . . . . . . 10-46
10-31 Take Address and Transfer Data Primitive Format . . . . . . . . . . . . . . . . . . 10-48
10-32 Transfer To/From Top of Stack Primitive Format. . . . . . . . . . . . . . . . . . . . 10-49
10-33 Transfer Single Main Processor Register Primitive Format . . . . . . . . . . . . 10-50
10-34 Transfer Main Processor Control Register Primitive Format . . . . . . . . . . . 10-51
10-35 Transfer Multiple Main Processor Registers Primitive Format . . . . . . . . . . 10-52
10-36 Register Select Mask Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52
10-37 Transfer Multiple Coprocessor Registers Primitive Format . . . . . . . . . . . . 10-53
To Next Page
Loading...
Need help?
General
