Bus Operation
7-62 MC68030 USER’S MANUAL MOTOROLA
If the appropriate cache is not enabled or if the cache freeze bit for the cache is set, the
processor does not assert CBREQ
. CBREQ is not asserted during the read or write cycles
of any read-modify-write operation.
The MC68030 allows burst filling only from 32-bit ports that terminate bus cycles with
STERM and respond to CBREQ
by asserting CBACK. When the MC68030 recognizes
STERM
and CBACK and it has asserted CBREQ, it maintains AS, DS, R/W, A0–A31, FC0–
FC2, SIZ0–SIZ1 in their current state throughout the burst operation. The processor
continues to accept data on every clock during which STERM
is asserted until the burst is
complete or an abnormal termination occurs.
CBACK
indicates that the addressed device can respond to a cache burst request by
supplying one more long word of data in the burst mode. It can be asserted independently
of the CBREQ
signal, and burst mode is only initiated if both of these signals are asserted
for a synchronous cycle. If the MC68030 executes a full burst operation and fetches four
long words, CBREQ
is negated after STERM is asserted for the third cycle, indicating that
the MC68030 only requests one more long word (the fourth cycle). CBACK
can then be
negated, and the MC68030 latches the data for the fourth cycle and completes the cache
line fill.
The following conditions can abort a burst fill:
• CIIN
asserted,
• BERR
asserted, or
• CBACK
negated prematurely.
The processing of a bus error during a burst fill operation is described in 7.5.1 Bus Errors.
For the purposes of halting the processor or arbitrating the bus away from the processor with
BR
, a burst operation is a single cycle since AS remains asserted during the entire
operation. If the HALT
signal is asserted during a burst operation, the processor halts at the
end of the operation. Refer to 7.5.3 Halt Operation for more information about the halt
operation. An alternate bus master requesting the bus with BR
may become bus master at
the end of the operation provided BR
is asserted early enough to be internally synchronized
before another processor cycle begins. Refer to 7.7 Bus Arbitration for more information
about bus arbitration.
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