Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-69
Since CIIN, CBACK, and STERM are synchronous signals, they must meet the
synchronous input setup and hold times for all rising edges of the clock while AS is
asserted. If STERM
is negated at the beginning of S2, wait states are inserted after S2,
and STERM
is sampled on every rising edge of the clock thereafter until it is recognized.
Once STERM
is recognized, data is latched on the next falling edge of the clock
(corresponding to the beginning of S3).
State 3
The processor maintains AS
, DS, and DBEN asserted during S3. It also holds the address
valid during S3 for continuation of the burst. R/W
, SIZ0–SIZ1, and FC0–FC2 also remain
valid throughout S3.
The external device must keep the data driven throughout the synchronous hold time for
data from the beginning of S3. The device must negate STERM
within one clock after
asserting STERM;
otherwise, the processor may inadvertently use STERM prematurely
for the next burst access. STERM
need not be negated if subsequent accesses do not
require wait cycles.
State 4
At the beginning of S4, the processor tests the level of STERM
. This state signifies the
beginning of burst mode, and the remaining states correspond to burst fill cycles. If
STERM
is recognized, the processor latches the incoming data at the end of S4. This data
corresponds to the second long word of the burst. If STERM
is negated at the beginning
of S4, wait states are inserted instead of S4 and S5, and STERM
is sampled on every
rising edge of the clock thereafter until it is recognized. As for synchronous cycles, the
states of CBACK
and CIIN are latched at the time STERM is recognized. The assertion
of CBACK
at this time indicates that the burst operation should continue, and the assertion
of CIIN
indicates that the data latched at the end of S4 should not be cached and that the
burst should abort.
State 5
The processor maintains all the signals on the bus driven throughout S5 for continuation
of the burst. The same hold times for STERM
and data described for S3 apply here.
State 6
This state is identical to S4 except that once STERM
is recognized, the third long word of
data for the burst is latched at the end of S6.
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