Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-79
Another signal that is used for bus exception control is HALT. This signal can be asserted
by an external device for debugging purposes to cause single bus cycle operation or (in
combination with BERR
) a retry of a bus cycle in error.
Figure 7-48. Breakpoint Acknowledge Cycle Timing (Exception Signaled)
CLK
A31-A0
FC2-FC0
R/W
ECS
OCS
AS
DS
DSACK0
DBEN
SIZ1-SIZ0
DSACK1
S0 S2 S4 S0
S2
HALT
SwSw Sw
S4
D31-D0
BERR
READ WITH BUS ERROR ASSERTED
INTERNAL
PROCESSING
STACK WRITE
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