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MC68030
Motorola MC68030 User Manual
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Introduction
1-2
MC68030 USER’S MANUAL
MOTOROLA
Figure 1-1. Block Diagram
MICROSEQUENCER AND
CONTROL
CONTROL
STORE
INSTRUCTION
CACHE
STAGE
B
STAGE
C
STAGE
D
INTERNAL
DATA
BUS
INSTRUCTION PIPE
INSTRUCTION
ADDRESS
BUS
ADDRESS
SECTION
PROGRAM
COUNTER
SECTION
DATA
SECTION
EXECUTION UNIT
MISALIGNMENT
MULTIPLEXER
SIZE
MULTIPLEXER
DATA
PADS
DATA
BUS
WRITE PENDING
BUFFER
PREFETCH PENDING
BUFFER
MICROBUS
CONTROLLER
BUS CONTROLLER
BUS CONTROL
SIGNALS
ADDRESS
BUS
ADDRESS
PADS
ADDRESS
BUS
ADDRESS
DATA
CACHE
DATA
ADDRESS
BUS
CACHE
HOLDING
REGISTER
(CAHR)
ACCESS
CONTROL
UNIT
CONTROL
LOGIC
24
26
Table of Contents
Default Chapter
4
Table of Contents
4
Adapting the MC68030 to MC68020 Designs
21
Microsequencer
22
Features
26
MC68030 Extensions to the M68000 Family
27
Programming Model
27
Translation Table Structure
31
Data Types and Addressing Modes
32
Instruction Set Overview
32
Virtual Memory
34
Virtual Memory and Virtual Machine Concepts
34
Virtual Machine
36
The Memory Management Unit
37
Pipelined Architecture
38
The Cache Memories
38
Data Organization and Addressing Capabilities
39
Instruction Operands
39
Memory Management Unit
39
Organization of Data in Registers
40
Data Registers
40
Address Registers
42
Control Registers
42
Organization of Data in Memory
43
Addressing Modes
46
Data Register Direct Mode
47
Address Register Direct Mode
48
Address Register Indirect Mode
48
Address Register Indirect with Postincrement Mode
48
Address Register Indirect with Predecrement Mode
49
Address Register Indirect with Displacement Mode
50
Address Register Indirect with Index (8-Bit Displacement) Mode
50
Address Register Indirect with Index (Base Displacement) Mode
51
Memory Indirect Postindexed Mode
52
Memory Indirect Preindexed Mode
53
Program Counter Indirect with Displacement Mode
54
Program Counter Indirect with Index (8-Bit Displacement) Mode
54
Program Counter Indirect with Index (Base Displacement) Mode
55
Program Counter Memory Indirect Postindexed Mode
56
Program Counter Memory Indirect Preindexed Mode
57
Absolute Short Addressing Mode
58
Absolute Long Addressing Mode
58
Immediate Data
59
Effective Address Encoding Summary
60
Coprocessor Instruction Format
60
Format
61
Programmer`s View of Addressing Modes
62
Addressing Capabilities
63
Format
63
General Addressing Mode Summary
70
M68000 Family Addressing Compatibility
74
Other Data Structures
74
System Stack
74
Format
74
User Program Stacks
76
Queues
77
Instruction Set Summary
79
Instruction Format
79
Instruction Summary
80
Format
80
Format
81
Data Movement Instructions
82
Integer Arithmetic Instructions
83
Logical Instructions
84
Shift and Rotate Instructions
85
Bit Manipulation Instructions
86
Bit Field Operations
87
Binary-Coded Decimal Instructions
88
Program Control Instructions
89
System Control Instructions
90
Format
90
Memory Management Unit Instructions
91
Multiprocessor Instructions
91
Integer Condition Codes
92
Condition Code Computation
93
Conditional Tests
95
Instruction Set Summary
96
Scanpc
99
Instruction Examples
103
Using the CAS and CAS2 Instructions
103
Nested Subroutine Calls
108
Bit Field Operations
109
Pipeline Synchronization with the Nop Instruction
110
Processing States
111
Exceptions
111
Privilege Levels
112
Supervisor Privilege Level
112
User Privilege Level
113
Changing Privilege Level
114
Address Space Types
115
Exception Processing
116
Exception Vectors
116
Protocol Violations
116
Exception Stack Frame
117
Signal Description
118
Interrupts
118
Signal Index
119
Address Bus (A0-A31)
121
Data Bus (D0-D31)
121
Function Code Signals (FC0-FC2)
121
Transfer Size Signals (SIZ0, SIZ1)
121
Bus Control Signals
122
Operand Cycle Start (OCS)
122
External Cycle Start (ECS)
122
Read/Write (R/W)
122
Read-Modify-Write Cycle (RMC)
122
Address Strobe (AS)
122
Data Strobe (DS)
123
Data Buffer Enable (DBEN)
123
Data Transfer and Size Acknowledge (DSACK0, DSACK1)
123
Synchronous Termination (STERM)
123
Cache Control Signals
124
Cache Inhibit Input (CIIN)
124
Cache Inhibit Output (CIOUT)
124
Cache Burst Request (CBREQ)
124
Cache Burst Acknowledge (CBACK)
124
Bus Arbitration Control Signals
125
Bus Request (BR)
125
Bus Grant (BG)
126
Bus Grant Acknowledge (BGACK)
126
Interrupt Control Signals
125
Interrupt Priority Level Signals
125
Interrupt Pending (IPEND)
125
Autovector (AVEC)
125
Bus Exception Control Signals
126
Reset (RESET)
126
Halt (HALT)
126
Bus Error (BERR)
126
Emulator Support Signals
127
Cache Disable (CDIS)
127
MMU Disable (MMUDIS)
127
Pipeline Refill (REFILL)
127
Internal Microsequencer Status (STATUS)
127
Clock (CLK)
128
Power Supply Connections
128
Signal Summary
128
On-Chip Cache Memories
130
Instruction Cache
130
On-Chip Cache Organization and Operation
132
Protection
132
Instruction Cache
133
Registers
134
Data Cache
135
Write Allocation
137
Read-Modify-Write Accesses
138
Cache Filling
138
Single Entry Mode
138
Burst Mode Filling
142
Cache Control
144
Cache Control Register
144
Write Allocate
145
Data Burst Enable
145
Clear Data Cache
145
Clear Entry in Data Cache
145
Freeze Data Cache
146
Enable Data Cache
146
Instruction Burst Enable
146
Clear Instruction Cache
146
Clear Entry in Instruction Cache
146
Freeze Instruction Cache
147
Enable Instruction Cache
147
Cache Address Register
147
Bus Operation
148
Cache Reset
144
Bus Transfer Signals
148
Bus Control Signals
150
Address Bus
151
Address Strobe
151
Data Bus
152
Data Strobe
152
Data Buffer Enable
152
Bus Cycle Termination Signals
152
Data Transfer Mechanism
153
Dynamic Bus Sizing
153
Misaligned Operands
160
Effects of Dynamic Bus Sizing and Operand Misalignment
166
Address, Size, and Data Bus Relationships
169
MC68030 Versus MC68020 Dynamic Bus Sizing
171
Cache Filling
171
Cache Interactions
172
Asynchronous Operation
174
Synchronous Operation with Dsackx
175
Synchronous Operation with STERM
176
Data Transfer Cycles
177
Asynchronous Read Cycle
178
Asynchronous Write Cycle
184
Asynchronous Read-Modify-Write Cycle
191
Synchronous Read Cycle
196
Synchronous Write Cycle
199
Memory Interface
199
Synchronous Read-Modify-Write Cycle
202
Burst Operation Cycles
207
CPU Space Cycles
216
Interrupt Acknowledge Bus Cycles
217
Interrupt Acknowledge Cycle - Terminated Normally
218
Autovector Interrupt Acknowledge Cycle
219
Spurious Interrupt Cycle
222
Breakpoint Acknowledge Cycle
222
Coprocessor Communication Cycles
222
Bus Exception Control Cycles
223
Bus Errors
230
External Caches
231
Retry Operation
237
Halt Operation
239
Double Bus Fault
242
Bus Synchronization
243
Bus Arbitration
244
Bus Request
246
Bus Grant
247
Bus Grant Acknowledge
248
Bus Arbitration Control
248
Reset Operation
251
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Motorola MC68030 Specifications
General
Brand
Motorola
Model
MC68030
Category
Computer Hardware
Language
English
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