Bus Operation
7-106 MC68030 USER’S MANUAL MOTOROLA
The external RESET signal resets the processor and the entire system. Except for the initial
reset, RESET
should be asserted for at least 520 clock periods to ensure that the processor
resets. Asserting RESET
for 10 clock periods is sufficient for resetting the processor logic;
the additional clock periods prevent a reset instruction from overlapping the external RESET
signal.
Figure 7-63. Bus Arbitration Operation (Bus Inactive)
A31-A0
FC2-FC0
ECS
OCS
AS
DS
DSACK1
CLK
S4 S0
SIZ1-SIZ0
R/W
DSACK0
DBEN
BGACK
BG
BR
D31-D0
CONTROLLER CONTROLLERALTERNATE MASTER
BUS INACTIVE
(ARBITRATION PERMITTED
WHILE THE CONTROLLER IS
INACTIVE OR HALTED)
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