68P81083C20-D December 6, 2004
Controller Section Theory of Operation: MicroprocessorOperation 7-13
The external EEPROM (U0100) as well as the µP’s own internal EEPROM space contain the
information in the radio which is customer specific, referred to as the codeplug. This information
consists of items such as: 1)what band the radio operates in, 2)what frequencies are assigned to
what channel, and 3) tuning information. In general, tuning information and other more frequently
accessed items are stored in the internal EEPROM (space within the 68HC11F1), while the
remaining data is stored in the external EEPROM. (See the particular device subsection for more
details.)
The external SRAM (U0101) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM (U0102) contains the actual Radio Operating Software. This software is
common to all radios within a given model type. For example Securenet radios may have a different
version of software in the FLASH ROM than a non-secure radio (See the particular device
subsection for more details).
The µP provides an address bus of 16 address lines (A0-A15), and a data bus of 8 data lines (D0-
D7). There are also 5 control lines; CSPROG (U0103-53), CSGEN (U0103-54), CSI01 (U0103-55),
E CLK (U0103-34), and RWBIN (U0103-35). CSPROG and CSI01 are used to chip select the SLIC,
CSGEN is used to chip select the SRAM. E CLK and RWBIN are used to generate the proper timed
control signals to the memory devices. E CLK is generated by the microprocessor based on µP CLK
and is always 1/4 the frequency of µP CLK, e.g. if µP CLK is 7.3728 MHz, then E CLK will be 1.8432
MHz.
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 4.8 and 5.0 V, and the logic low levels
should be between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and
fall times should be <30 ns.
The low-order address lines (A0-A4) and the data lines (D0-D7) should be toggling at a high rate, e.
g., you should set your oscilloscope sweep to 1 us/div. or faster to observe individual pulses. High
speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U0103-51), BOOTSTRAP (U0103-58) and RESET (U0103-50) should be
high at all times during normal operation. However, the XIRQ line is a non maskable interrupt and
can be low during interrupt. Whenever a data or address line becomes open or shorted to an
adjacent line, a common symptom is that the RESET line goes low periodically, with the period being
in the order of 20 msecs. In the case of shorted lines you may also detect the line periodically at an
intermediate level, i.e. around 2.5 V when 2 shorted lines attempt to drive to opposite rails.
The MODA (U0103-33) and MODB (U0103-32) inputs to the µP must be at a logic 1 for it to start
executing correctly. After the µP starts execution it will periodically pulse these lines. While the
Central Processing Unit (CPU) is running, this signal is an open-drain CMOS output which goes low
whenever the µP begins a new instruction (an instruction typically requires 2-4 external bus cycles,
or memory fetches). However, since it is an open-drain output, the waveform rise assumes an
exponential shape similar to an RC circuit.
There are 8 analog to digital converter ports (A/D) on U0103. They are labelled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5 V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action. For example U0103-23 is the battery voltage detect line. R0417 and R0416 form
a resistor divider on SWB+. With 68K and 22K and a voltage range of 11 V to 17 V, that A/D port
would see 2.68 V to 4.15 V which would then be converted to ~136 to 211 respectively.
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