National Instruments PCI E Series - Page 159

Index
PCI E Series RLPM I-8
© National Instruments Corporation
Number_of_Scans function
AMUX-64T examples
sampling one channel, 4-27
scanning eight channels, 4-30
analog triggering example, 4-55
STC scanning examples, 4-12
with DMA, 4-18
with external start and stop
trigger, 4-23
with external start trigger and scan
start, 4-21
with interrupts, 4-15
single wire acquisition, 4-25
O
operation of PCI E Series boards. See theory of
operation.
OUT signal, timing I/O circuitry, 2-25
Output<D..A> bits, 3-22
P
PCI E Series boards. See also theory of
operation.
block diagrams
PCI-6023E, PCI-6024E, and
PCI-6025E, 2-3
PCI-6032E and PCI-6033E, 2-4
PCI-MIO-16E-1, PCI-MIO-16E-4,
and PCI-6071E, 2-1
PCI-MIO-16XE-10,
PCI-MIO-6052E, and
PCI-6031E, 2-2
PCI-MIO-16XE-50, 2-5
characteristics, 1-1 to 1-2
list of boards, xiii
PCI interface circuitry, 2-6 to 2-7
block diagram, 2-7
description, 2-6
PCI local bus programming considerations,
4-1 to 4-4
PCI initialization
for IBM compatible systems, 4-2
for Macintosh computers, 4-4
re-mapping PCI E Series board, 4-3 to 4-4
PFIO/TRIG1 signal, 4-53
PGIA (programmable gain instrumentation
amplifier)
analog trigger programming
considerations, 4-53
gain selection with Gain<2..0> bits, 3-10
gain set versus board (table), 2-9 to 2-10
theory of operation, 2-9
posttrigger acquisition, 2-18 to 2-19
pretrigger acquisition, 2-18 to 2-19
programmable gain instrumentation amplifier
(PGIA). See PGIA (programmable gain
instrumentation amplifier).
programming
analog triggering, 4-52 to 4-56
DMA programming, 4-57 to 4-59
DMA structure (figure), 4-57
Link Chaining Mode for DMA
transfer, 4-58 to 4-59
examples. See programming examples.
general-purpose counter/timer,
4-45 to 4-52
interrupt programming, 4-56
interrupt sharing, 4-56 to 4-57
PCI local bus, 4-1 to 4-4
PCI initialization
for IBM compatible systems, 4-2
for Macintosh computers, 4-4
re-mapping PCI E Series board,
4-3 to 4-4
RTSI trigger lines considerations, 4-52
windowing registers, 4-5