Index
PCI E Series RLPM I-10
©
National Instruments Corporation
re-mapping PCI E Series board, 4-3 to 4-4
RTSI bus interface circuitry
block diagram, 2-26
theory of operation, 2-25 to 2-26
RTSI trigger lines, programming
considerations, 4-52
RTSI_BRD0 signal, 4-52
S
sample interval (SI2), 2-12
scan counter (SC), 2-12 to 2-13
scan interval (SI), 2-12
SCAN sequence
definition, 2-12
starting, 2-13
scanning, multirate. See multirate scanning.
SerClk bit
connection to EEPROM clock, 5-1
connection to serial DAC clock, 5-15
description, 3-4
SerDacLd0 bit
connection to serial DAC clock, 5-15
description, 3-4
SerDacLd1 bit
connection to serial DAC clock, 5-15
description, 3-4
SerDacLd2 bit
connection to serial DAC clock, 5-15
description, 3-4
SerData bit
connection to EEPROM clock, 5-1
connection to serial DAC clock, 5-15
description, 3-4
Serial Command Register
description, 3-4
register map, 3-2
Setup_Mite function
analog input examples
acquiring one sample from
channel 0, 4-9
digital I/O examples, 4-7
general-purpose counter/timer examples
gated event counting, 4-45
initializing PCI
IBM compatible systems, 4-2
Macintosh computers, 4-4
re-mapping PCI E Series board, 4-3
setvect() function, 4-14
SHIFTIN* signal, ADC timing, 2-12
Simple_Gated_Count function, 4-45
single-point output, analog output timing
circuitry, 2-22 to 2-23
single-read timing, data acquisition timing
circuitry, 2-11 to 2-12
SOURCE signal, timing I/O circuitry, 2-25
START signal, 2-13
START1 signal, 2-18
START2 signal, 2-18
Status Register
description, 3-6
register map, 3-2
STOP signal, 2-13
support files for example programs, 4-6
T
technical support, A-1 to A-2
telephone and fax support numbers, A-2
theory of operation
analog input circuitry, 2-8 to 2-11
analog output circuitry, 2-21 to 2-22
analog output timing circuitry,
2-22 to 2-24
single-point output, 2-22 to 2-23
waveform generation, 2-23 to 2-24
analog triggering, 2-19 to 2-20
block diagrams
PCI-6023E, PCI-6024E, and
PCI-6025E, 2-3
PCI-6032E and PCI-6033E, 2-4
To Next Page
Loading...
