NEC FD1165 - 3.6 Interface Timing

-1 r- 125 ns ± 10%
READ DATA (ROT) ------.....,U
u
(MFM)
0.5T +0.5T
T=1Jls10%
(FM) T ------l .....
Figure 3-9 Read Data and Window Signal Timing
3.6 INTERFACE TIMING
This section describes the interface timing for the Model
FDl165.
3.6.1 Power On Sequence
The FDl165 processes valid I/O signals 700 ms after the door
is closed.
3.6.2 Drive Select
The disk drive processes valid I/O signals 500 ns after the
Drive Select line (DX) goes Low.
3.6.3 Step and Track 00
Figure 3-10 shows the required time relationship between the
Step signal from the controller and the Track 00 output
signal.
STP----"""":U
u
TRO ----------t-----,
T -I T - 2.5 ms (MAX)
Figure 3-10 Step and Track 00 Timing
3-10