Nexo NXAMP4X1

NXAMP4x1
NXAMP4x1
7
NXAMP4x1
BACDEFGH
2
1
3
4
5
28CA1-2001022111-40
SW[1,2]
GPI[0:4],
ES_GPI[1:3]
/RESET_DSP1,3,
/RESET_ADCDAC,
/RESET_SENSE,
/RESET_VOLUME
TEMP_PS_A[1,2],
/GPO_CS
/GPI_CS
/CSIO[0]
/SW2_CS
/CSIO[4,5]
CSIO[6,7]
UI_DATA[7:0]
/CSIO[5:7],
CSIO[6,7]
/GPI_CS
/GPO_CS
/UI_CS
LCD_ENABLE
/SW1_CS
LCD_ENABLE
/ES_CS
/DSP1_CS
/DSP3_CS
/SW1_CS
/SW2_SC
/UI_CS
/ETH_CS
40MHz
+3.3D
+3.3D
Serial Flash ROM
16Mbit
CPU
UPSD3354
SDA
SCL
TEMP_PA[1:4]
MAINS_A
/PSW_DETECT
RS232_TX,RX
ES_TX,RX
LV4052
+3.3D
GPO[0:7]
+3.3D
RELAY_PS_A[1:2],
SHUTDOWN_PS_A
/CSIO[1]
FAN_CONTROL[1:2]
RELAY_PA[1:4]
RELAY_OUT[1:4]
/CSIO[2]
/CSIO[3]
SOURCE_SEL
/MUTE_VOLUME
+5D
+3.3D
+1.25D
-15A -9A
+15A +9A
+5A
ENC[1,2]
+1.25V reg
-9V reg
+9V reg
ENCODERx1
LEDx79
KEY x 10
+5D
+3.3D
LVC541
HCT273
x2
+5D
HCT4514
x4
SCLK
LRCK
DSP
ADSP56371
SPI_I/F
/DSP1_CS
+3.3D+1.25D
/RESET_DSP1
CODEC0_DIGI_OUT
CODEC1_DIGI_OUT
ES_I2S_DATA0
ES_I2S_DATA1
CODEC0_DIGI_IN
SENSE_I12_DIGI_OUT
SENSE_U12_DIGI_OUT
MCLK,SCLK,LRCK
SENSE_U12_DIGI_OUT
SENSE_I12_DIGI_OUT
SENSE_U34_DIGI_OUT
SENSE_I34_DIGI_OUT
MCLK,SCLK,LRCK
MCLK,SCLK,LRCK
MCLK,SCLK,LRCK
/RESET_SENSE
/RESET_SENSE
/RESET_SENSE
/RESET_SENSE
+5A+3.3D
A/D 2ch
PCM1803A
A/D 2ch
PCM1803A
A/D 2ch
PCM1803A
A/D 2ch
PCM1803A
RELAY_OUT[1:4]
+15A-15A
SENSE_U1
SENSE_U2
SENSE_U3
SENSE_U4
SENSE_I1
SENSE_I2
SENSE_I3
SENSE_I4
See page 6
See page 4
ANA_IN1
ANA_IN2
ANA_IN3
ANA_IN4
ANA_OUT1
ANA_OUT2
ANA_OUT3
ANA_OUT4
TEMP_PA[1:4],CLIP_PA[1:4]
RELAY_PA[1:4]
Analog Volume
8ch
CS3318
-9A
-15A
SDA
SCL
CODEC 2ch/2ch
CS4272
+5A+3.3D +15A
+5A+3.3D
/RESET_VOLUME
/MUTE_VOLUME
CODEC0_DIGI_OUT
CODEC0_DIGI_IN
MCLK,SCLK,LRCK
SDA
SCL
/RESET_ADCDAC
CODEC1_DIGI_OUT
MCLK,SCLK,LRCK
/RESET_ADCDAC
CODEC1_DIGI_IN
SDA
SCL
CODEC0_DIGI_OUT
CODEC1_DIGI_OUT
ES_I2S_DATA0
ES_I2S_DATA1
CODEC1_DIGI_IN
SENSE_I34_DIGI_OUT
SENSE_U34_DIGI_OUT
DSP
ADSP56371
/DSP3_CS
SPI_I/F
SCLK
LRCK
/RESET_DSP3
+3.3D+1.25D
See page 5
TX
RX
GPO_[0:7]A
GPI[0:4]
OPTION SLOT
EtherSound
RS232
GPI
See page 6
+3.3D
+5D
RS232_TX,RX
GPO[0:7]
SPI_I/F
ES_TX,RX
+5D
/ES_CS
/ETH_CS
ES_GPI[1:3]
/RESET
SOURCE_SEL
ES_MCLK,ES_SCLK,ES_LRCK
ES_I2S_DATA[1:0]
CLOCK BLOCK
24.576
MHz
INT_MCLK,INT_SCLK,INT_LRCK
SOURCE_SEL
MCLK
SCLK
LRCK
LVC157
+9A+3.3D
CS4272
CODEC 2ch/2ch
PN-AN
PSANL
CONTROL RS232-GPI
PAANL
INANL
OUTANL
OPT-AN
■ BLOCK DIAGRAM 4/5