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Since the FPGA on the Nexys A7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This
configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device
upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a nonvolatile flash device,
a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash
devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools).
This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent
power-on or reset event as determined by the mode jumper setting (see Figure 3). Programming files stored in the flash device will remain
until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory
technology. Once written however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and
configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Nexys A7 supports x1, x2, and x4 bus
widths and data rates of up to 50 MHz () for Quad-SPI programming.
Quad-SPI programming can be done using the iMPACT tool included with ISE or the Lab Tools version of Vivado.
You can program the FPGA from a pen drive attached to the USB Host port (J5) or a microSD card inserted into J1 by doing the following:
1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the Nexys A7.
4. Set the JP1 Programming Mode jumper on the Nexys A7 to “USB/SD”.
5. Select the desired storage device using JP2.
6. Push the PROG button or power-cycle the Nexys A7.
The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7
device will be rejected by the FPGA.
The Auxiliary Function Status, or “BUSY” LED (), gives visual feedback on the state of the configuration process when the FPGA is not
yet programmed:
When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or pen
drive) and downloading a bitstream to the FPGA.
A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
In case of an error during configuration, the LED () will blink rapidly.
When the FPGA has been successfully configured, the behavior of the LED () is application-specific. For example, if a USB keyboard is
plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.
The Nexys A7 board contains two external memories: a 1Gib (128MiB) DDR2 SDRAM and a 128Mib (16MiB) non-volatile serial Flash
device. The DDR2 modules are integrated on-board and connect to the FPGA using the industry standard interface. The serial Flash is on a
dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are shown below.
The Nexys A7 includes one Micron MT47H64M16HR-25:H DDR2 memory component, creating a single rank, 16-bit wide interface. It is
routed to a 1.8V-powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal
terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for
impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design.
There are two recommended ways to do that, which are outlined below and differ in complexity and design flexibility.
The straightforward way is to use the Digilent-provided DDR-to-SRAM adapter module which instantiates the memory controller and uses
an asynchronous SRAM bus for interfacing with user logic. This module provides backward compatibility with projects written for older
Nexys-line boards featuring a CellularRAM instead of DDR2. It trades memory bandwidth for simplicity.
More advanced users or those who wish to learn more about DDR SDRAM technology may want to use the Xilinx 7-series memory
interface solutions core generated by the MIG (Memory Interface Generator) Wizard. Depending on the tool used (ISE, EDK or Vivado),
the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of
several DDR parameters optimized for the particular application. Table 3.1 below lists the MIG Wizard settings optimized for the Nexys
A7.
2.3 USB Host and Micro SD Programming
3 Memory
3.1 DDR2
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