Nokia 9000i - Functional Description; Introduction; Clocking Scheme; Reset and Power Management

After Sales
Technical Documentation
RAE/RAK–1N
PDA Hardware
Page 6 – 18
Original, 08/96
Functional Description
Introduction
Intel E3G is 386 based core with all needed peripherals on same chip.
E3G is used to execute all applications, GEOS, DOS, BIOS, and TFFS.
Clocking Scheme
Actual clock signals are not routed to any other chip than previously
mentioned E3G. All clocks are generated from a 32.768 kHz chrystal with
PLL’s integrated to the E3G CPU chip.
System clock rates are as follows:
CPU core 23.96 MHz
UART’s 1.84MHz
8254 Timer 1.198MHz
RTC 32.768kHz
Reset and Power Management
Power good (PWRGOOD) signal from PDAPWRU module is used as a
system reset. Both PDA and CMT modules power management system is
implemented with special hardware in close co–operation with operating
system.
Figure 2. Reset and power management block diagram
5 V Power supply
LCD Power supply
3.3 V Power supply
POWER SUPPLY
RESET
LCDPVEEON
I/O
PWRGOOD
I/O
I/O
IR tranceiver
RS232 Buffer
Shutdown
Shutdown
1M x 16
FLASH
PowerDown
I/O
5VPDX
PMI
LID SWITCH
GND
E3G
CPU
Integrated CPU
LCDVCCON
1M x 16
FLASH
PowerDown
PMI
VL1
SUS–
PEND
”XIP” FLASH FLASH file system
LCDPVEEON
LCDVCCON
LIDOPEN (CMT)
Enable
Note 1.