After Sales
Technical Documentation
RAE/RAK–1N
Faultfinding/Disassembly
Page 8 – 43
Original, 05/97
Appendix B
POST progress codes. These are written during POST to the IO address
2FFh, and if the BIOS–testmode is entered the last code is copied to the
IO address 3FFh.
00h POST beginning
01h CPU register test starting
05h Disabling shadowing & cache
0Dh Test CMOS RAM shutdown register
0Eh Check CMOS checksum, update DIAG byte
11h Disable interrupts controllers
12h Disable Port B and video display
13h Initialize chipset and start auto memory detect
15h Test 8254 Timer2 for speaker, Port B
16h Test 8254 Timer1 for refresh
17h Test 8254 Timer0 for 18.2Hz
18h Start memory refresh
1Ah Test 15 us refresh ON/OFF time
19h Test memory refresh
20h Test address lines
22h Base 64kB memory read/write test
23h System initialization before vector table init
24h Initialize vector table
35h Check ROM BIOS data area at segment 40h
40h Prepare virtual memory test, verify from display memory
42h Enter virtual mode for memory test
44h Initialize data for checking wraparound at 0:0
4Ch Clear extended memory for soft reset
4Dh Save memory size
53h Save registers & memory size, enter real–mode
55h Disable A20 line
66h Initialize interrupt controllers
82h Initialize circular buffer
84h Check for memory size mismatch (CMOS/BIOSDATA)
8Fh Configure floppy drives
94h Set base & extended memory sizes
95h Memory size adjusted for 1k, verify display memory
96h Initialization before calling C800h
97h Call ROM BIOS extensions at C800h
98h Processing after extension returns
99h Configure timer data area
A6h Enable NMIs
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