Nokia 9000i - Block Description; Memory Map

After Sales
Technical Documentation
RAE/RAK–1N
Baseband
Page 2–23
Original, 08/96
Block description
– MCU Memories
The MCU has a 20 bits wide address bus A(19:0) and an 16–bit data bus
with memories. The address bits A(19:13) are used for chip select
decoding. The decoding is done inside the SCL in CTRLU submodule.
Hitachi HD6475388 processor has internal ROM and RAM memories.
Memory Map
Table 26. Memory Map
PAGE ADDRESS FPAGE[1:0]= 00 FPAGE[1:0]=01 FPAGE[1:0]=10
0
00000
0EE7F
INTERNAL ROM
60 Kbytes (16 bit)
0EE80
0F67F
EXTERNAL ADDRESS
SPACE
0F680
0FE7F
INTERNAL RAM
2 Kbyte (16 bit)
0FE80
0FFFF
REGISTER FIELD
384 bytes
1 10000
1FFFF
RAM
64 Kbytes (16 bit)
2 – 11 20000
BFFFF
FLASH
640 Kbytes (16 bit)
FA[19:17]=001...101
12 – 13 C0000
DFFFF
FLASH
128 Kbytes (16 bit)
FLASH page 0
FA[19:17]=110
FLASH
128 Kbytes (16 bit)
FLASH page 1
FA[19:17]=111
FLASH
128 Kbytes (16 bit)
FLASH page 2
FA[19:17]=000
14
E0000
EDFFF
SRAM
56 Kbytes (16 bit)
EE000
EFFFF
EEPROM
8 Kbytes (8 bit)
15 F0000
F001A
FFFFF
ASIC
26 bytes (8 bit)