Nokia 9000i - I;O Map

After Sales
Technical Documentation
RAE/RAK–1N
PDA Hardware
Page 6 – 35
Original, 08/96
Table 20. I/O usage on E3G CPU
Signal name E3G CPU pin Polarity Reset value
PWRGOOD RESET# H = Power good – (In)
5VPDX PMI2 / P45 L = Shut down L
TESTMODEX (Input) DTR0# / P02 L = Test mode – (In)
IRSHD RI1# / P13 H = Shut down H
RSSHDX DSR0# / P00 L = Shut down H
RSENX CTS0# / P04 L = Enabled H
XPWRON PMI3 / P44 H (pulse) => CMT ON L
FLASHPD1X SUSPEND# L = Shut down H
FLASHPD2X RI0# / P03 L = Shut down H
FLASHWP1X DCD0# / P01 L = Protected H
FLASHWP2X CTS1# / P15 L = Protected H
LCDVCCON LCDVCCON H = Vcc ON L
LCDVEEON LCDVEEON H= Vee ON L
DISPON DISPON H = Display ON L
”LID” PMI0 H = Lid open – (In)
VL1 PMI1 H = CMT ON – (In)
I/O map
All chipselects are generated in the E3G.
Table 21. I/O Map
Device Address Note
PIC0 0020 – 0021 Standard PC compatible
PIC0 F022h Edge / Level control E3G Spe-
cific
Timers 0 – 2 0040h – 0043h Standard PC compatible
Port B 0061h Standard PC compatible
RTC Offset 0070h Standard PC compatible
RTC Data 0071h Standard PC compatible
Port 92 0092h Standard PC compatible
PIC1 00A0h – 00A1h Standard PC compatible
PIC1 F0A2h Edge / Level control E3G Spe-
cific
COM2 02F8h – 02FF Standard PC compatible
COM1 03F8h – 03FF Standard PC compatible
DRAM controller F300h – F323h E3G Specific
IRDA Select Register F3F8h – F3F9h E3G Specific