After Sales
Technical Documentation
RAE/RAK–1N
PDA Hardware
Page 6 – 27
Original, 08/96
DRAM area is composed of a single 1M x 16 bit chip. The access time of
70 ns enables zero wait–state page access and one wait–state page fault.
FLASH memory is used for two purposes on this device. Two 1M x 16 bit
chips (75 ns) are used for BIOS, DOS, GEOS and applications this
memory is usually called XIP FLASH. A 1M x 16 bit chip (120 ns) is used
to save user data. This memory device is handled by FLASH file system.
From application point of view this memory is accessed like hard disk
using INT13 functions. 75 ns FLASH device needs one wait–state and
120 ns device two wait–states.
FLASH devices are equipped with Reset/Power down pin (RP#) which can
be used to place devices in a Deep PowerDown state. RP# pin of two XIP
FLASH devices is connected to SUSPEND pin of E3G. SUSPEND# pin is
active when E3G is in SUSPEND mode and internal PLL’s are not runnig.
RP# pin of the FLASH device under TFFS is connected to a GPIO pin and
it is controlled by TFFS. TFFS and RS232 flash download softwares are
able to control 5V power supply powerdown. There is 100us delay needed
between 5V power up and write command.
1 Mbyte of address space is directly addressable by the CPU
(conventional memory). Any additional memory is accessed via Expanded
Memory System EMS . EMS system follows LIM 4.0 specification.
Memory Map
Table 18. Memory Map
000000
00FFFF
Interrupt Vector, DOS data (DRAM)
010000
07FFFF
GEOS heap (DRAM)
09E400
0A03FF
True FFS data (DRAM)
0A0400
0A05FF
BIOS data (DRAM)
0A0600
0AFFFF
Video buffer (DRAM)
0B0000
0B3FFF
EMS page 0 (True FFS & GEOS ROM
disk)
0B4000
0B7FFF
EMS page 1 (XIP page 2)
EMS register
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