After Sales
Technical Documentation
RAE/RAK–1N
PDA Hardware
Page 6 – 33
Original, 08/96
– Chip selects
E3G CPU has four programmable chip selects. Size of the memory block
can be defined with 2K resolution. Start address can be changed in 2K
boundaries. These chip selects have independent programmable wait
states (0–64).
Table 19. FLASH Chip Select Generation
A
2
5
A
2
4
A
2
3
A
2
2
A
2
1
A
2
0
A
1
9
A
1
8
A
1
7
A
1
6
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
CHIP
SELECT
NOTES
1 1 1 1 1 X X X X X X X X X X UCS XIP
FLASH 1.
0 0 0 0 0 0 1 1 X X X X X X X UCS XIP
FLASH 1.
Double map-
ping
1 1 1 1 0 X X X X X X X X X X CS0 XIP
FLASH 2.
1 1 1 0 1 X X X X X X X X X X CS1 RFD
FLASH 1.
DRAM controller enables shadowing in the area of 640KB – 1MB in
16–Kbyte granularity. Each block of memory can be configured as being
disabled, read–only, write–only, or read/write. Unused memory in the area
of 640KB – 1MB can be rolled over in 64–Kbyte granularity. Roll–over
base is selectable in 512–Kbyte granularity.
– FLASH programming
PDA module FLASH memories can be programmed in two ways. During
the manufacturing JTAG interface of the E3G CPU is used to download
FLASH image to FLASH devices. For aftersales and R&D purposes BIOS
is equipped with FLASH download capability via RS232. JTAG method is
needed at aftersales as a backup.
During the manufacturing it is not possible to use any download method
that needs CPU involvement because there is no any program code for
execution on the device. JTAG interface was selected for this purpose
because it exists on the E3G CPU and it is a standard. In principle JTAG
interface is able to set CPU signals (address, data, etc.) to requested
state. By changing signal values in reasonable manner FLASH writing is
possible. Special hardware is needed for JTAG FLASH download during
manufacturing as well as for aftersales purposes. JTAG FLASH download
system is integrated to PTS and maintenance software.
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