After Sales
Technical Documentation
RAE/RAK–1N
Baseband
Page 2–36
Original, 08/96
Table 37. External Signals and Connections, Outputs (continued)
ToSignal descriptionSignal Name
DSPCLKEN DSP clock circuit enable DSPU
RFICLK RFI master clock (13 MHz) RFI
RFI2CLK RFI sleep clock (135.4 kHz) RFI
CODEC_CLK PCM data clock (512 kHz) DSPU, AU-
DIO
PCMDATRCLKX Inverted PCM data clock (512 kHz)
used as input clock for Codec and DBUS interface
DSPU
SYNC Bit sync clock (8 kHz) AUDIO
PCMCOSYCLKX Bit sync clock (8 kHz), inverted DSPU
DCLK DBUS data clock (512 kHz) DSPU
DSYNC DBUS bit sync clock (8 kHz) DSPU
SIMCLK SIM data clock (3.25/1.625 MHz) SIMFLEX
Conn.
VSIM SIM power control SIMFLEX
Conn.
COL(3:0) Lines for keyboard column write B2B Conn.
Table 38. External Signals and Connections, Bidirectional
Signal Name Signal description To/From
DSPDA(15:0) DSP’s 16–bit data bus DSPU
MCUDA(15:8) MCU’s 8–bit data bus CTRLU
RFIDA(11:0) RFI’s 12–bit data bus RFI
UIF(6:0) LCD–controller control and keyboard read bus B2B Conn.
SIMDATA Serial data from/to SIM SIMFLEX
Conn.
Block description
PSL+ supplies the reset to the ASIC at power up. The ASIC starts the
clocks to the DSP and the MCU. MCU and RFI reset is released after 256
13 MHz clock cycles. DSP reset release time from DSP clock activation
can be selected from 0 to 255 13MHz clock cycles. In our case 255 is
selected. SIM reset release time is according to GSM SIM specifications.
The RFC buffer buffers the 26 MHz clock from theVCXO to the ASIC. In
the ASIC the clock is further buffered and delivered to MCU. The clock is
also divided and delivered to RFI and SIM. ASIC also generates main and
sync clocks for audio codec, DSP‘s SIOs and DBUS. The clock outputs
can be disabled in order to save current when the clock is not needed.
Also the 60.2 MHz DSP oscillator can be disabled by the ASIC.
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