Hardware description
For trace, a footprint for a 20-pin connector is available (P25). If trace functionality is required, it is
possible to mount a 2×10 pin 1.27 mm pitch surface mount pin header.
GPIO Trace Default use
P0.12 TRACECLK
P0.11 TRACEDATA[0]
P0.10 TRACEDATA[1]
P0.09 TRACEDATA[2] Button 4
P0.08 TRACEDATA[3] Button 3
Table 7: Default and Trace GPIOs
The reference voltage for the debug input and trace is by default connected to VDD_nRF'. This can be
connected to the VDD by cutting SB60 and soldering SB59.
5.10 Debug output
The nRF5340 PDK board supports programming and debugging external boards with nRF51 or nRF52 SoCs.
To debug an external board with SEGGER J-Link OB IF, connect to the Debug out connector (P19) with a 10-
pin cable.
Figure 27: Debug output connector
When the external board is powered, the interface MCU will detect the supply voltage of the board and
program/debug the target chip on the external board instead of the onboard nRF5340 SoC.
Note: The voltage supported by external debugging/programming is VDD voltage. Normally, this
is 3 V when running from USB, but if the onboard nRF5340 SoC is supplied from either USB or Li-
Ion, the nRF power source switch (SW9) is in either Li-Po or USB position, and VDD can be set by
the nRF5340 firmware. Make sure the voltage level of the external board matches the VDD of the
nRF5340 PDK.
You can also use P20 as a debug out connection to program shield-mounted targets. For both P19 and
P20, the interface MCU will detect the supply voltage on the mounted shield and program/debug the
target.
If the interface MCU detects target power on both P19 and P20, it will by default program/debug the
target connected to P19.
4406_489 v1.0
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