Display
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 31
Figure 7-1. DSI 1 x 2 Lane Connection Example
Jetson
Tegra
DS I/CSI
DSI_A_CLK_P
DSI_A_CLK_N
Display
Connector (DSI)
D0P
D0N
D1P
D1N
CLKP
CLKN
DSI_A_D0_P
DSI_A_D0
_N
DSI_A_D1_P
DSI_A_D1
_N
SYS LCD_BL_PWM
Optional Backlight PWM
78
76
72
70
84
82
DSI_CLK_P
DSI_CLK_N
DSI_D0_P
DSI_D0_N
DSI_D1_P
DSI_D1_N
GP IO 07
206
Note: If EMI/ESD devices are necessary, they must be tuned to minimize impact to signal quality,
which must meet the DSI spec. requirements for the frequencies supported by the design.
7.1.1 MIPI DSI and CSI Design Guidelines
Table 7-3 details the MIPI DSI and CSI interface signal routing requirements.
Table 7-3. MIPI DSI and CSI Interface Signal Routing Requirements
Parameter Requirement Units Notes
Max frequency/data rate (per data lane)
DSI
CSI
750 / 1500
1250 / 2500
MHz/Mbps
Number of loads 1 load
Reference plane
GND
Trace impedance (Diff pair / SE) 90-100 / 45-50 Ω
±10%
Via proximity (signal to reference) < 0.65 (3.8) mm (ps)
Intra-pair trace spacing 0.15mm mm Can be adjusted to meet
Differential Impedance. Loosely
Coupled Diff. Pair
recommended by Spec.
Inter-pair trace spacing (Microstrip / Stripline) 4x / 3x dielectric
Max PCB breakout length 5 mm
Insertion Loss
1 Gbps
1.5 Gbps
2.5 Gbps
3.0
2.9
1.92
dB
Max trace delay
1 Gbps
1.5 Gbps
2.5 Gbps
421 (2526)
319 (1913)
150 (900)
mm (ps)
Max intra-pair skew 1 ps
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