Nvidia Jetson TX2 NX User Manual

Miscellaneous Interfaces
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 60
11.2 SPI
The Jetson TX2 NX brings out two of the Tegra X2 SPI interfaces. See Figure 11-2.
Table 11-4. Jetson TX2 NX SPI Pin Description
Pin # Module Pin Name Tegra X2 Signal Usage/Description
Usage on DevKit
Carrier Board
Direction Pin Type
89 SPI0_MOSI GPIO_WAN7 SPI 0 Master Out / Slave In
Expansion header Bidir CMOS – 1.8V
91 SPI0_SCK GPIO_WAN5 SPI 0 Clock
93 SPI0_MISO GPIO_WAN6 SPI 0 Master In / Slave Out
95 SPI0_CS0* GPIO_WAN8 SPI 0 Chip Select 0
97 SPI0_CS1*
GPIO_MDM4
(SPI1_CS1 SFIO)
SPI 0 Chip Select 1
104 SPI1_MOSI
GPIO_SEN3
(SPI2_DOUT SFIO)
SPI 1 Master Out / Slave In
106 SPI1_SCK
GPIO_SEN1
(SPI2_CLK SFIO)
SPI 1 Clock
108 SPI1_MISO
GPIO_SEN2
(SPI2_DIN SFIO)
SPI 1 Master In / Slave Out
110 SPI1_CS0*
GPIO_SEN4
(SPI2_CS0 SFIO)
SPI 1 Chip Select 0
Notes:
1. In the Type/Dir column, Output is from Jetson TX2 NX. Input is to Jetson TX2 NX. Bidir is for Bidirectional signals.
2. The directions for SPI[1:0]x are true when used for those functions. Otherwise as GPIOs, the directions are bidirectional.
Figure 11-2. SPI Connections
Jetson
Tegra – SPI
UART
SPI0_SCK
SP I 0_M I SO
SP I 0_M OSI
SP I 0_CS0 *
SP I 0_CS1 *
SPI1_SCK
SP I 1_M I SO
SP I 1_M OSI
SP I 1_CS0 *
GPIO _WAN5
GPIO _WAN6
GPIO _WAN7
GPIO _WAN8
GPIO _MDM4
Routed to 40-pin
Expansion Header on
DevKit carrier board
91
89
93
95
97
GPIO _SEN1
GPIO _SEN2
GPIO _SEN3
GPIO _SEN4
106
104
108
110
AO

Nvidia Jetson TX2 NX Specifications

General

Brand	Nvidia
Model	Jetson TX2 NX
Category	Computer Hardware
Language	English