Nvidia Jetson TX2 NX - Page 49

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NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 41
Parameter Requirement Units Notes
The traces after main route via should be routed as 100Ω differential or as uncoupled 50ohm SE traces on PCB
top or bottom.
Max distance from RPD to main trace (seg B) 1 mm
Max distance from AC cap to RPD stubbing point (seg A) ~0 mm
Max distance between ESD and signal via 3 mm
Add-on Components
Example of a case where space is limited for placing
components.
Top: See Figure 7-12 Bottom: See Figure 7-13
AC Cap
Value 0.1 uF
Max via distance from BGA 7.62 (52.5) mm (ps)
Location must be placed before pull-down resistor
The distance between the AC cap and
the HDMI connector is not restricted.
Placement
PTH design
Micro-via design
Place cap on bottom layer if main-route
above core
Place cap on top layer if main-route below
core
Not Restricted
Void
GND (or PWR) void under/above the cap is
needed. Void size = SMT area + 1x dielectric
height keepout distance
See Figure 7-14
Pull-down Resistor (RPD), choke/FET
Value 500 Ω
Location. Must be placed after AC cap Placement: See Figure 7-15
Layer of placement
Same layer as AC cap. The FET and choke
can be placed on the opposite layer thru a
PTH via
Choke between RPD and FET
choke
Max trace Rdc
Max trace length
600 or
1
≤20
4
Ω @ 100 MHz
uH@DC-100 MHz
mΩ
mm
Can be choke or Trace.
Recommended option for HDMI2.0
HF1-9 improvement.
Void GND/PWR void under/above cap is preferred
Common-mode Choke (Not recommended – only used if absolutely required for EMI issues)
See Appendix A for details on CMC if implemented.
ESD (On-chip protection diode can withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option)
Max junction capacitance (IO to GND) 0.35 pF
e.g. Texas Instruments
TPD4E02B04DQAR
Footprint Pad right on the net instead of trace stub See Figure 7-16
Location After pull-down resistor/CMC and before RS
Void
GND/PWR void under/above the cap is
needed. Void size = 1mm x 2mm for 1 pair
See Figure 7-17
Series Resistor (RS) – Series resistor on N/P path for HDMI 2.0 (mandatory)
Value ≤ 6 Ω
± 10%. 0ohm is acceptable if the
design passes the HDMI2.0 HF1-9
test. Otherwise, adjust the R
S value to
ensure the HDMI2.0 tests pass: Eye
diagram, Vlow test and HF1-9 TDR
test
Location
After all components and before HDMI
connector
Void
GND/PWR void under/above the R
S device is needed. Void size = SMT area + 1x
dielectric height keepout distance.