NXP Semiconductors MPC5748G - Page 30

D
C
B
5
4
3
2
1
Ethernet (Configured for MII Mode)
All Ethernet Signals are in power
domain VDD_HV_B
The Ethernet
interface only supports
3V3_SR
L51
3V3_SR
120OHM
3.3V operation. All I/O signals must
1
2
be 3.3V. If VDD_HVA is set to 5V,
Layout Note - Place Caps
Ethernet MCU pads must be left as
and Resistors close to PHI
tri-state
with no pullups.
C71
C73
R12
R11
C81
C79
0.1UF
0.1UF
0.1UF
(MII Clock)
10UF
(0603
2.2K
2.2K
(0603
(0603
C15
(Bulk
5%
5%
R13
3V3_SR
Storage)
50V)
50V)
50V)
49.9
33PF
2
2 2
3248
2021
1%
Y1
GND
10/100 single phy
33PF
25MHZ
U8
AVDD33
IOVDD33 1IOVDD332
RSVDPU1RSVDPU2
GND
GND
1
R23
0
C10
3V3_SR
Pulse J1011F21PNL
(RMII)
CLKIN_X1
34
X1
R14
0.1UF
(0603
(Includes built in
C14
(+MII)
X2
33
X2
49.9
transformer)
7
PG13
PG13
R104
50
(+MII)
TXD3
6
25MHZ_OUT
25
TPV17
1%
50V)
1
P5
RJ45-8
TXD3_SNIMODE
TD+
7
PG12
PG12
R105
50
(+MII)
TXD2
5
TXD2
TDP
17
TDP
GND
2
TD-
GND1
CG1
7
PH0
PH0
R106
50
(RMII)
TXD1
4
TXD1
TDN
16
TDN
3
CT_3
7
PH1
PH1
R107
50
(RMII)
TXD0
3
TXD0
4
GND_4
7
PH2
PH2
R108
50
R32
50
(RMII)
TXEN
2
TXEN
14
RDP
5
GND_5
7
PG1
PG1
(RMII)
TXCLK
1
TXCLK
RDP
6
CT_6
dp83848c
13
RDN
3V3_SR
7
GND2
CG2
7
PE13
PE13
R31
50
(+MII)
RXD3
46
RDN
R15
8
RD+
RXD3_PHYAD3
RD-
7
PA7
PA7
R30
50
(+MII)
RXD2
45
RXD2_PHYAD2
49.9
Y A Y C
G C G A
7
PA8
PA8
R29
50
(RMII)
RXD1
44
RXD1_PHYAD1 LEDACTCOL_ANEN
28
LED_Y
1%
7
PA9
PA9
R28
50
(RMII)
RXD0
43
RXD0_PHYAD1
LEDLINK_AN0
26
LED_G
9 1 0
1112
7
PF15
PF15
R24
50
(RMII)
RXDV
39
RXDV_MIIMODE LEDSPEED_AN1
27
GND
GND
7
PA11
PA11
R26
50
(RMII)
RXER
41
RXER_MDIXEN
C11
C8
C7
7
PA10
PA10
R27
50
(+MII)
COL
42
COL_PHYAD0
PFBOUT
23
PFBOUT
0.1UF
0.1UF
0.1UF
7
PE12
PE12
R25
50
(RMII)
CRS
40
CRS/CRS_DV/LED_CFG
18
R16
(0603
(0603
(0603
R4
R5
7
PA3
PA3
R22
50
(+MII)
RXCLK
38
RXCLK
PFBIN1
49.9
37
1%
50V)
50V)
50V)
270
270
7
PG0
PG0
R109
50
(RMII)
MDC
31
MDC
PFBIN2
7
PF14
PF14
MCU Output
PHI Output
(RMII)
(MDIO)
30
MDIO
GND
3V3_SR
3V3_SR
GND
Resistors Next
Place Next to
29
RESET
Place Caps close
to MCU on
PHI
7
PWRDN_INT
RBIAS
24
RBIAS
to connector
daughtercard
AGN D 1
AGND 2
DGNDIOGND 1IOGND2
RSVD1RSVD2RS VD3RSVD4R SVD5
Series Termination Resistors:
R10
50 Ohms as per TI spec. Place
4.87K
resistors as close to driving
Layout Note:
source as possible. Termination
1915363547
89101 112
recommended for ALL MII signals
Place 0.1uF cap close to each pin.
GND
C72
C74
C75
C80
10uF TANT as close to pin 23 as
RST-OUTx
R82
50
0.1UF
0.1UF
+
0.1UF
possible as shown in diagram below
5
RST-OUTx
GND
(0603
(0603
10UF
(0603
taken from TI device specificaiton
8
PI11
PI11
R83
0
50V)
50V)
(TANT)
50V)
DNP
PFBIN1
PFBIN2
PFBOUT
3V3_SR
Reset Control:
R84
- Reset from MCU Reset Out (will reset with MCU)
GND
10.0K
- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in reset
while reset config data can be driven onto pins to change mode etc.
D
C
B
A
Boot Configuration (using PHY internal Pulls)
- Auto Negotiation Enable (All speeds / duplex
supported) (AN_EN, AN0 and AN1 all Internal PullUP)
- Operating Mode (MII)
(SNI_Mode Internal PullDown, MII_Mode control via PF15)
- LED Configuraiton (Mode1)
(LED_CFG Internal PullUp)
- MDIX Enable (Auto MDIX Enabled)
(MDIX_EN Internal PullUP)
- Physical Address (set to 0b00001)
(PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown)
Layout Note:
R110
PF15
2.2K 5%
(MII_MODE)
GND Configured for MII Mode
3V3_SR MDIO Pullup
R113 1.5K PF14
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
A
MII Mode resistor and the MDIP ullup resistor should be placed as close as possible to
the PF15 / PF14 tracks to reduce the effect of a stub on the transmission line.
Page Title:
Ethernet
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 12
of
15
5 4 3 2 1
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