107
operand bits in the step are turned OFF and all timers in the step are reset to
their SVs. Counters, shift registers, and bits used in KEEP(12) maintain sta-
tus. Two simple steps are shown below.
SNXT(05) 0200
STEP(04) 0200
0000
Step controlled by 0200
SNXT(05) 0201
STEP(04) 0201
0001
Step controlled by 0201
SNXT(05) 0202
STEP(04)
0002
Starts step execution
Ends step execution
1st step
2nd step
Address Instruction Operands Address Instruction Operands
000 LD 0000
001 SNXT(05) 0200
002 STEP(04) 0200
Step controlled by 0200.
030 LD 0001
031 SNXT(05) 0201
032 STEP(04) 0201
Step controlled by 0201.
051 LD 0002
052 SNXT(05) 0202
053 STEP(04) ---
Steps can be programmed in consecutively. Each step must start with
STEP(04) and generally ends with SNXT(05). When steps are programmed
in series, three types of execution are possible: sequential, branching, or par-
allel. The execution conditions for, and the positioning of, SNXT(05) deter-
mine how the steps are executed.
Interlocks and END(01) cannot be used within step programs.
Bits used as control bits must not be used anywhere else in the program un-
less they are being used to control the operation of the step.
If output bits, work bits, or LR bits are used for control bits, their status will be
lost during any power interruption. If it is necessary to maintain status to re-
sume execution at the same step, DR bits must be used.
0411: Step Start Flag; turns ON for one scan when STEP(04) is executed
and can be used to reset counters in steps as shown below if neces-
sary.
Precautions
Flags
Instruction Set Section 3-7
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