Panasonic KX-NS500AG - 4.2. Main Unit

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KX-NS500AG
4.2. Main Unit
The Main Unit is constructed by CPU Board (MPR) and Mother Board. The block diagram and operation of each card are
described here.
4.2.1. CPU Board (MPR)
Fig.2 shows detail block diagram of CPU Board (MPR) , and each function of CPU Board (MPR) is described in Table.4.
Table.4 CPU Board (MPR) Function Description
Device/Function Block Description
CPU CPU controls exchange and monitoring functions of the whole NS500 system.
DDR3 DDR3 is main memory of CPU Board (MPR). Operating system, application program and concerning data are
stored in this memory.
NAND Flash Program and system data are stored in this memory.
SRAM SRAM is backed up by battery, and system information is stored this non-volatilized memory.
FPGA FPGA provides basic PBX function such as time switch, tone generation and so on.
USB USB master port for maintenance.
L2SW/LAN(RJ45) LAN port is used for VoIP and Web-MC connection.
SD Card UM voice data are stored in this SD card.
RTC RTC is battery backed up clock which maintains system clock of NS500 system.
ARM
Cortex- A8
600MHz
L1 32K/32K w/SED
L2 256K w/ECC
176K ROM 64K RAM 64K RAM
Crypto
DDR
Interface
DDR3
512MB
NAND
NAND
FLASH
1GB
UART
McASP
Ethernet
USB
SD
GPIO
Interrupt
etc.
DC/DC(+3.3V,+1.8V,+1.1V)
I2C
AC_ALM, DC_ALM, System Reset, FPGA_REBOOT, DONE
EXP-M
Connector
DSP option
Connector
RMT Option
Connector
Master
FPGA
USB
TypeA
LAN
RJ45
RMII
USB- Host- I/F
SRAM
512KB
LED
RTC
+5V
External bus
ER,DR
SLIDE SW
SD-I/F
80PIN CONNECTOR (CPUInterface)
TDM
L2SW
PHY
STATUS
PBX MODE
PHY
PHY
DC/DC
+3.3V
+15V
8bit
8bit
16bit
SD-Card
Connector
16bit
+5V
+VBAT
Expansion bus
UART-I/F
+5V
Fig.2 CPU Board (MPR) Block Diagram