Panasonic TH-42PZ77U - DG-Board (2 of 4) Block Diagram

15.14. DG-Board (2 of 4) Block Diagram
XIRQ3
FE_IRQ
SDCD
SDCMD
SDWP
SDCLK
RMIN
R_LED_ON
KEY3
VI1CKOUT
VI1ENB
VI1VSYNC
VI1HSYNC
VI1CLK
DTV_DMIX
DTV_SRCK
DTV_LRCK
IECOUT0
CH0DATA
CH0PSYNC
CH0VAL
CH0CLK
SDCLK SDCMD
SDCD SDWP
SCL2
SDA2
AUDIO_MUTE
AUDIO_XRST
MAIN_PB
HDMI_INT2
HDMI_LRCK
HDMI_SDIN
HDMI_BCLK
SOY
MAIN_PR
MAIN_Y
DTV_SRCK
DTV_LRCK
DTV_DMIX
RF_L
RF_R
RF_V
KEY1
FAN_SOS
FAN_MAX
TV_SUB_ON
SOUND_SOS
A_MON_MUTE
HDMI_SPDIF
SOS
STB_RST
AI_SENSOR
DTV_XRST
DTV_V
DTV_V
D1120
D1113 D1112
STB3.3V
STB5V
D5613
D5614
BT30V DTV9V
L5612
D5612
D1111
Q5608
DG1
AI_SENSOR
9
7
SUB5V
1
R_LED_ON
RM_IN
KEYSCAN3
K1
TO
STB3.3V
2
3
5
(XIRQ2)FE-IRQ
(XIRQ3)HDMI-IRQ
XRST
XERE
XEWE0 XECS0
ED0
ED15
EA7 EA0
SDCLK
SDCD
SDCMD
SDWP
SDDATA0 SDDATA3
XESC1
BOOTSWAP
XEDK,XECLK
ESZ0,ESZ1
XEWE1
ERXW
XIRQ1,XNMIRQ
CPU BUS I/F
VI2CLK
VI2HSYNC
VI2VSYNC
EA8-EA23,EA24
ADDRESS
SUB VIDEO INPUT
VI2P12-19,VI2P22-29,VI2P4
VI1P2-9,VI1P12-19,VI1P22-29
ADV7493 INPUT
VI1ENB
VI1HSYNC
VI1VSYNC
VI1CKOUT
VI1CLK
ANALOG VIDEO I/F
MVDACO0
MVDACO1
MVDACO2
MVDACO3
C
V
Y
U
Y
B
G
R
COMP
COMP
COMP
CH0CLK
CH0VAL
CH0DATA
CH0PSYNC
CH I/F
LRCK0
DAUDIO
AUDIO I/F
DMIX0
SRCK0
IECOUT0
DACCK0
(PORT-B)
(PORT-A)
INPUT_I/F
DIGITAL
DIGITAL
AUDIO
PROCESSOR
I/F
DIGITAL
VIDEO
INPUT
AUDIO
SD CARD I/F
STB3.3V
SUB5V
SW_RESET
24
OUTVDD
24
OUTVCC
STB RESET
VINVOUT
54
STB 3.3V
Q5604
SUB5V
VDDEXT
VOUT
52
BT30V
1
Q5605
20
VB
Q5607
CB
D1
CTL
OUT1-1
21
-INC1
DTV9V
16
LX
23
VO1
SUB1.8V
Q5600
LX2
D2 D2
9V->1.2V,9V->1.8V
D1
OUT2-1
D2
S1
25
LX1
G1
D1
G1
FB1
OUT2
G1
OVP
19
27
VCC
24
26
Q5602
S1
24
D1
20
FB
Q5606
DC-DC CONVERTER
S1
-INC
VCC
OUT1-2
DTV9V
CB1
G2
16
CB2
S2
S2
4
21
SUB3.3V
12
23
8
G2
DC-DC CONVERTER
D1
3
7
17
VO
S2
D2
G2
OUT1
12
FB2
VO2
OUT2-2
9
Q5601
17
VB
D2
-INC2
15
19
SUB1.2V
CTL
18
11
30
8
D1
LSAT
D2
DTV9V
DTV9V
TRST TCK TDO(TO GC3FS) TDI TMS
JTAG
A23 A0 DQ0 DQ15
OE WE CE RESET
128 bit NOR FLASH
21
OUTVDD
RESET
DTV9V
JTAG
1
DG52
35 8 11712
SDCLK SDDTC SDCMD SDWP
SDDATA0 SDDATA3
IEC_OUT0
KEY1
27
FAN SOS
29
30
FAN MAX
SOS
43
45
GENX_RST
AUDIO_XRST
48
49
AUDIO_MUTE
46
A_MON_MUTE
SCL0B
51
53
SDA0B
SOUND_SOS
42
TV_SUB_ON
32
UV0-UV9,Y0-Y9,R0-R3
ADDRESS BUS
DIGITAL SIGNAL PROCESSOR
Peaks Lite2
H/V
CLK
R/G/B
71
74
55
9
HDMI BCLK
76
15
RGB_CVBS
DVB_CVBS
11
7
HDMI SDIN
HDMI INT2
MAIN_PR
SPDIF_IN(OPT)
13
MAIN_PB
HDMI LRCK
MAIN_Y
78
23
DTV_SDIN
DTV_LRCK
19
DTV_BCLK
21
39
RF_L
RF_V
35
RF_R
37
DG3
TO
H3
FHD9V
12
DG2
2
9
1
8
TO
H2
13
FHD9V
FHD9V
DTV9V
SUB5V
14
18
17
SUB3.3V
MAIN9V
23
21
STB5V
DTV9V
DTV9V
SUB5V
SUB5V
SUB5V
SUB3.3V
MAIN9V
SUB3.3V
STB5V
9V->3.3V
SCL
SDA
SUB3.3V
6
1
4
VDD
SDA1
SCL1
TO
GS52
IC1108
IC5602 IC5604
IC5605
IC5601
IC5600
IC8001
IC8502
IC5704
IC4054
TEMP SENSOR
HDMI INTERFACE
DIGITAL SIGNAL PROCESSOR
DG
MICOM
BT30V DET
SUB3.3V
(DLCTRL)ISODATA
SUB3.3V
2
1
3
4
11
12
13
FULL HD
LED BLINKING
TUNER SOS
:10TIMES
TH-42PZ77U
DG-Board (2 of 4) Block Diagram
TH-42PZ77U
DG-Board (2 of 4) Block Diagram
TH-42PZ77U
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