Panasonic TH-42PZ77U - D-Board (1 of 2) Block Diagram

15.31. D-Board (1 of 2) Block Diagram
STB+3.3V
PANEL POWER PART SOS DET
P+5V FAIL VOLTAGE LED BLINKING
5 TIMES
P+15V OVER VOLTAGE LED BLINKING
2 TIMES
P+3.3V FAIL VOLTAGE LED BLINKING
3 TIMES
READY
LED_R
STB_SDA2
LED_R
PSLCT
MAIN_ON
RXD
TXD
P_ON/OFF
PSTB
TXD
RM
SOS4
LED_G
LED_G
PDB1
MAIN_ON
PDB0
PBUSY
PBUSY
P3V_SDA1
ALARM
P3V_SCL1
STB_SDA2
PBUSY
P3V_SCL2
PSLCT
PSTB
P3V_SDA2
PSTB
CLKM
PDB0
ALARM
SOS4
RXD
STB_SCL2
STB_SCL2
P_ON/OFF
STB_SCL2
RM
PDB1
RXD
VDA
P3V_SDA1
P3V_SCL1
PDB0
TXD
READY
STB_SDA2
DRVMUTE
PDB1
VDA
P3V_SCL2
STB_SDA2
P3V_SDA2
STB_SCL2
P_CTL
WR_CTL
WR_CTL
XRST2
P3V_SDA1
P3V_SDA2
P3V_SCL2
P3V_SCL1
XRST
STBSDA2
STBSCL2
STB_SDA1
STB_SCL1 STB_SCL1
STB_SDA1
NRST2 NRST2 DRVMUTE PSLCT
SOS6_SC1 SOS7_SC2 SOS8_SS DRVRST
PRCK
Q9051
Q9054
P+1.2V
R9141
R9203
P+5V
Q9046
P+3.3V
Q9805
Q9806
Q9052
Q9044
Q9053
STB+5V
R9205
STB+5V
R9215
X9000
D9020
P+2.5V
Q9050
PA9800
P+15V
D9819
D9818
D9110
D9804
D9802
D9811
E+LVDS0
10
RX
RA_E+
S CLOCK2
VD
OSD_HD
LVDS
12
OSC
PROCESSOR
11
53
50
20
84MHz
STBY+5V
14
4
OSD_B
20
10bit
92
15
36
REMOTE
15
PANEL SOS DET
OSD_R
10bit
ON/OFF
49
IIC_CONT
1
OSD_GI
23
7
D6
90
10
STB+3.3V/RESET
PDB0
OSD_CLKI
P+15V
STB+3.3V
21
16
P+3.3V/P+1.2V
2
ASDIO
PROCESSOR
EEPROM(FPGA)
13
HD
32
M_VDO
6
3
S D ATA1
1
DISCHARGE
CONTROL
249
TXD
27MHz
P+15V DET SOS2
37
STB+3.3V
RC_E-
G
STB+3.3V
M_HD0
18
POWER SOS DET SOS4_PS
(LVDS_DET)
RXD
RC O-
P+15V
RCLK E-
ON/OFF
16
18
ECO_ON
17
LED R
DCLK
P25
PSLCT
OSD_CLKO
IIC_INT
IIC_CONT
PSTB
6
ON/OFF
OSD_G
2
86
PSLCT
P+3.3V
TXD
P+1.2V/P+2.5V/P+3.3V
21
6
RB O+
DISPEN
Vda SOS DET
33IIC_CONT
20MHz
OSD_BI
18
PBUSY
DATA CONTROL(U)
CONT
21
B
IIC_DATA2
+3.3V
D
PDB1
S DATA1_IIC1_SDA
SUS CONTROL
RESET
84
RD O+
8
54
PSTB
34
IIC
P+15V SOS DET
2
10
LVDS_DET
6
VD
5
DG35
+3.3V
D5
RA O+
LED G
OSD_RI
IIC/INT
DATA CONTROL(D)
18
16
PDB0
PARALLE
11
16
POWER STATUS READY
18
RXD
27
ALARM
9
RCLK O+
RA_E-
IIC_DATA1
70
RE O-
PDB1
SCAN CONTROL
IIC_CLK2
17
RB_E+
RC O+
DG5
TUNER_SUB_ON
PBUSY
PLASMA AI PROCESSOR
FOR
19
RD O-
FORMAT CONVERTER,
8
FACTORY USE
67
INV.
87
85
(1MB)
PSTB
72
HD
14
RC_E+
S CLOCK2_IIC2_SCL
TXD
30
P+5V SOS DET
21
PANEL MAIN ON/OFF
D3
RA O-
B
26
6
RESET
7
RE O+
10bit
69
NCS
S DATA2_IIC2_SDA
RD_E-
RD_E+
RE_E+
LED RED
12
4
DATA 0
66
S CLOCK1_IIC1_SCL
P+3.3V DET SOS3
RXD
1
11
SUSTAIN ENERGY RECOVERY SOS8_SS
23
10bit
43
RB_E-
3
25
S D ATA2
LED GREEN
P+1.2V P+2.5V/P+3.3V ON/OFF
2
2
29
25
13
5
P+15V
RE_E-
31
STBY+5V
267
22
REMOTE
1
4
F_STBY_ON
Q9010
TTL
ECO ON
14
P+5V
P15V
15
PBUSY
1
READY
PANEL_MAIN_ON
STBY5V
5
RCLK O-
93
VDATA_DET
71
MICOM
ALL_OFF
29
R
ALL_OFF
PSLCT
SOS4_PS
G
IIC_INT
91
7
RB O-
PANEL_STBY_ON
RCLK E+
1917
PDB1
IIC_CLK1
P+5V DET SOS5
1
20
R
PDB0
17
10bit
D25
10bit
412
100
28
S CLOCK1
23
SYNC
DATA
79
19
SCAN ENEGRY RECOVERY SOS6_SC1
15
RGB
PICTURE
OUTPUT
(L)
(R)
PICTURE
OUTPUT
FLASH
CONTROL
(64k)
THERMAL SENSOR
1
EEPROM
6
P+3.3V
STB+3.3V
6
5
7WP
XOUT
XIN
NRST2
ALARM
SC FLOATING PART SOS7_SC2
PANEL_STBY_ON
P_CTL
VCC4
8
35 EEP_WR_CTL
LSI_RST
1
NRST
31D5_DET0
3
DRIVER_RESET
XCE_L
P+3.3V
P+2.5V
P+1.2V
P+5V
+1.2V
IC9805
Q9807,Q9808
Q9809
+2.5V
IC9806
P+2.5V
SCL
SDASDA
SCL
VCC
30P+5V
XRST24
8
11
6
3
13
1
4
10
9
12
14
2
5
IC9013
IIC SW
DCDC_ON
IC9007
VCC
7
VCC
3
8
VCC
STB+3.3V
27DCLK
DATA 0
ASDIO
28
26
29NCS
DCLK
DATA 0
ASDIO
NCS
P+1.2V
TDO
TRST
D9
3
TDI TMS
P+3.3V
27165
TCK
5
NRST2
D5_DET0
42LVDS_DET
OSD_YSI16OSD_YS
20
OSD_VD
HD
VD
SCL SDA
NRST2
DRV_MUTE NRST
DRIVER RESET
(INTERNAL
FREE RUN)
E-LVDS0
E+LVDS1
E-LVDS1 E-LVDS2
E+LVDS3
E-LVDS3
E+LVDS2
E+LVDSCLK
E+LVDS4
E-LVDS4
O+LVDSCLK
E-LVDSCLK
LVDS_DET
O+LVDS0
O-LVDSCLK
O-LVDS0
O+LVDS1
O-LVDS1
O+LVDS2
O-LVDS2
O+LVDS3
O-LVDS3
O+LVDS4
O-LVDS4
RE_E+ RE_E- RD_E+ RD_E- RC_E+ RC_E- RB_E+ RB_E- RA_E- RA_E+
RCLK_E+ RCLK_E-
LVDS_DET
RCLK_O+ RCLK_O-
RE_O+ RE_O- RD_O+ RD_O- RC_O+ RC_O- RB_O+ RB_O- RA_O+ RA_O-
SCAN CONTROL(42)
P+15V
JTAG
HD,VD
IC9011
IC9001
IC9002
IC9500
IIC_CONT
IIC_CONT
IIC
IC9003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
FPGA
FACTORY USE
FOR
TH-42PZ77U
D-Board (1 of 2) Block Diagram
TH-42PZ77U
D-Board (1 of 2) Block Diagram
TH-42PZ77U
95