Panasonic TH-42PZ77U - DG-Board (4 of 4) Block Diagram

15.16. DG-Board (4 of 4) Block Diagram
PEAKS_OSHO
PEAKS_OSCKO
HSIA
VSIA
CLKIA
HQ1_XRST
CONFIG_DONE
PEAKS_OSDCK
PEAKS_OSDH
OSD_FLAG
PEAKS_YS
PEAKS_YM
PEAKS_OSVO
TV_MAIN_ON
TV_MAIN_ON
FPGA_XRST
0-LVDS3
GC5P_1st
DDR-SDRAM
TMS
BA0,BA1
RE O+
0-LVDS2
IC5102
TDI(TO_HQ1L)
10
FRCK_FPGA
0+LVDS4
AVDD_DDRCLK
TCK
PEAKS_OSHO
1
0-LVDS0
NRST
7RC_E-
E+LVDSCLK
TRST
5
4
0-LVDSCLK
VS0E
TDO
D2
2
E+LVDS1
CONF_DONE
FHD3.3V
20
4
1
D1
DG4
5
OUT1-1
SCL
PEAKS_OSDH
0-LVDS4
VOUT
6
21
SDA
E+LVDS4
DDR 2.5V
15
-INC1
WP
E+LVDS3
IC5002
14
SUB(FHD)9V
E-LVDS1
VDD
12
23
DAC_VDD
VO1
SDA
VDD_PLL2
FHD3.3V
SCL
PEAKS_YS
VDD_PLL1
23
LX2
FHD3.3V
VDD12
18
9V->1.2V,9V->3.3V
64k EEPROM
VDD
OUT2-1
IC5000
AVR 3.3V
S1
21
IC5001
25
DQS0-DQS3
LX1
17
VOUT
0+LVDS2
D1
26
RD O+
PEAKS_OSVO
E+LVDS0
G1
25
6
E-LVDS2
FB1
29
5
OSDI0-7
DQ0-DQ31
G1
0+LVDS3
OSDI8-15
20
RAS,CAS
7
OVP
0+LVDSCLK
28
8
27
ROE0-9
30
VCC
VSIA
PEAKS_OSDCK
24
GOE0-9
WC
16
BOE0-9
RD_E+
SDA_MC
SCL_MC
31
RCLK O+
0+LVDS0
OUT1-2
SDA
0+LVDS1
PEAKS_YM
CB1
0-LVDS1
SCL
G2
CE
RB O+
OSD_FLAG
CB2
VS0E
FHQCIN0-9
FACTORY
CE
IC5901
FOR
FHD3.3V
AVDD_DDR
E-LVDS0
S2
USE
1
FRCK02
E-LVDS4
VDDA_PLL_DDR
4
VOUT
12
FRCLKIN
XTALIN
AVR 2.5V
8
27MHz
X5000
IC5009
G2
VIN
D1
XTALOUT
8
3
THQCO0-9
VDD25
VDDI01
7
PEAKS_OSCKO
THQYO0-9
S2
VDDI02
D2
THQHOUT
FB2
THQVOUT
VO2
NCFG
PEAKS
CLK0THQ1
OUT2-2
OSD0-15
E+LVDS2
RD O-
Q5901
VDDI04
FHQYIN0-9
E-LVDSCLK
RE_E-
17
SDCLK0,NSDCL0
4
FHQCKIN
RA_E-
VB
FHD3.3V
RC_E+
FHQHIN
D2
DQS0-DQS3
IC5013
IC5010
RCLK E-
-INC2
FHQVIN
VDD
19
RESET
FHD1.2V
OUT
FHD3.3V
RB_E-
CTL
2
18
RB O-
IC5012
VDD
CK,CK
1
PORT-A
11
RC O-
AVR 2.5V
VOUT
IC5008
CKE,WE
30
RA O+
VIN
A0-A11
5
D1
RE O-
D2
RAS,CAS
RCLK E+
AVR 3.3V
HS0E
PTVEN
FHD9V
RCLK O-
3
HSI
AVR 1.5V
RA O-
CLKID
VCC
(OUTPUT
VOUT
PORT-THQ
26
IC5006
PORT-E
RE_E+
8
Q5902
VOUT
FOR PANEL)
TDO
VCCINT
24
DQ0-DQ31
5
TMS
VCCA_PLL1
S1
RA_E+
1
ADDRESS BUS
1
VCCA_PLL2
A0-A11
FHD3.3V
CONFIG ROM
DATA BU S
3
TCK
VDDI03
TO D5
CONTROL BUS
SUB5V
CFG-JTAG
2
LVDS_DET
JTAG
IC5100
8
1
VSI
VCC
DATA O
RB_E+
SCL0
IC5105
(H264)
VDD
FHD3.3V
nCSO
RD_E-
NRST
CKE,WE
SDA0
FPGA
DATA
5
RC O+
SDA
CLK0ECLK0E
(CYCLONE)
HSIA
SCL
NCS1
5
FHD1.2V
ROE0-9
CLKIA
PORT-D
DCLKDCLK
11
HS0E
16
RVIA0-7
ASDIASDO
BOE0-9
VDDQ
(ADV)
BUIA0-7
3
6
GOE0-9
BA0,BA1
GYIA0-7
VDD
2
DG5
SDA0
PTVEN
9
E-LVDS3
SCL0
DC-DC CONVERTER
MHSYNC-HSIA
MVCLK-CLKIA
MVSYNC-VSIA
ROE2-RVIA1BOE2-GYIA3 GOE2-RVIA3
BOE3-GYIA1
BOE4-GYIA4
BOE5-GYIA0
BOE7-GYIA6
BOE6-GYIA7
BOE8-GYIA2
BOE9-GYIA5
GOE3-BUIA3
GOE4-BUIA7
GOE5-BUIA4
GOE8-RVIA5
GOE9-RVIA6
GOE7-RVIA7
ROE3-BUIA1
ROE5-RVIA2
ROE4-BUIA0
ROE7-RVIA0
ROE6-BUIA2
ROE8-RVIA4
ROE9-BUIA5
GOE6-BUIA6
PEAKS_OSD0-OSD15
VDDW
TDI
24
23
22
21
FULL HD
DIGITAL SIGNAL PROCESSOR
DG
MICOM
HDMI INTERFACE
TH-42PZ77U
DG-Board (4 of 4) Block Diagram
TH-42PZ77U
DG-Board (4 of 4) Block Diagram
TH-42PZ77U
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