Philips 19PFL5522D - Page 97

Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 97LC7.2E LB 9.
9.11.11 Diagram TT, Type THC63LVD824 (IC2), LVDS Receiver
Figure 9-22 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
H_17170_037.eps
250507
SERIAL TO PARALLEL
PLL
SERIAL TO PARALLEL
PLL
28
28
DEMUX
RA1 +/-
RB1 +/-
RC1 +/-
RD1 +/-
RCLK1 +/-
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
R/F
/PDWN
(25 to 135MHz)
RCLK2 +/-
(25 to 85MHz)
1st Link
8
8
8
8
8
8
RED1
GREEN1
BLUE1
HSYNC
VSYNC
DE
RED2
GREEN2
BLUE2
RECEIVER CLOCK OUT
(25 to 85MHz)
1st DATA
2nd DATA
CMOS/TTL OUTPUT
2nd Link
LVDS INP U T
LVDS GND
RA1-
RA1+
RB1-
RB1+
LVDS VCC
RC1-
RC1+
RCLK1-
RCLK1+
RD1-
RD1+
LVDS GND
RA2-
RA2+
RB2-
RB2+
LVDS VCC
RC2-
RC2+
RCLK2-
RCLK2+
RD2-
RD2+
LVDS GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R15
GND
VCC
R14
R13
R12
R11
R10
GND
VCC
CLKOUT
B27
B26
B25
B24
B23
GND
VCC
B22
B21
B20
G27
GND
VCC
G26
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PLL GND
PLL VCC
GND
/PDWN
MODE0
MODE1
GND
R/F
DRVSEL
R20
R21
R22
R23
R24
VCC
GND
R25 R26 R27
G20 G21
G22
G23
G24
G25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17 18 19 20 21
22
23
24 25
DE
VSYNC
HSYNC
B17
B16
GND
VCC
B15
B14
B13
B12
B11
B10
G17
G16
G15
G14
G13
GND
VCC G12 G11
G10
R17
R16
75 74
73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56 55
54
53
52
51