Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 142 Q528.2E LB9.
9.5.3 Diagram B03B, TDA10048HN (IC7T17-1)
Figure 9-9 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
H_16800_127.eps
090507
SCL_TUN
SDA_TUN
SCL, SDA
SADDR
MPEG TS
DO[7:0]/S_DO
(parallel/serial)
GPIO[3:0]
REB
C
REBV
R
O
C
NU_TPC
CHANNEL DECODER
confidence
(I,Q)
I
2
C-BUS
INTERFACE
DSP CORE SYNCHRONISATION
TDA10048HN
FREQUENCY, TIME, FRAME RECOVERY
FFT WINDOW POSITIONING
TPS DECODING
CHANNEL ESTIMATION
AND CORRECTION
VIM
VIP
XIN
XOUT
ΣΔ ΣΔ
ΣΔΣΔ
PLL
OSCILLATOR
TIME
INTERPOLATION
CPE
CALCULATION
PARTIAL
CHANNEL
ESTIMATION
FREQUENCY
INTERPOLATION
CHANNEL
CORRECTION
CONFIDENCE
CALCULATION
MPEG-2
OUTPUT
INTERFACE
DE-
SCRAMBLER
RS
DECODER
OUTER
FORNEY
DE-
INTERLEAVER
VITERBI
DECODER
BIT
DE-
INTERLEAVER
DEMAPPER
INNER
FREQUENCY
DE-
INTERLEAVER
ADC
ANALOG
DIGITAL FRONT-END
AND OFDM
DEMODULATION
AGC_TUN AGC_IF
FFT
2K / 4K / 8K
DYNAMIC
TIMESHIFT
CCI
CANCELLER
DIGITAL
AGC
TIME
RECOVERY
ACI
FILTERING
COARSE
TIME
ESTIMATOR
CARRIER
RECOVERY
DUAL
AGC
ΣΛ
STEP INTERFACE
ΣΛ
STEP INTERFACE
TDA10048HN
DO5
V
DDA(PLL)(1V2)
V
DDDC(1V2)
DO6
V
SSA(PLL)
DO7
V
DDA(OSC)(1V2)
V
DDD(3V3)
VTUOX
SSD
VNIX
SSDC
V
SSA(OSC)
V
DDDC(1V2)
V
DDD(ADC)(3V3)
GPIO0
V
SSA(ADC)
SADDR
ADSPIV
LCSMIV
V
DDA(ADC)(3V3)
TRST_N
V
SSDC
V
SSD
SDA_TUN
SCL_TUN
PSYNC/S_PSYNC
DEN/S_DEN
OCLK/S__OCLK
DO0/S_UNCOR
DO1/S_DO
DO2/GPIO1
DO3/GPIO2
DO4/GPIO3
V
DDD(ADC/PLL)(1V2)
V
SSD(ADC/PLL)
V
DDD(3V3)
V
DDDC(1V2)
V
SSDC
AGC_TUN
AGC_IF
CLR_N
TDO
TCK
TDI
TMS
12 25
11 26
10 27
928
829
730
631
532
433
334
235
136
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
terminal 1
index area
Transparent top view
To Next Page
Loading...
