Philips pm2521 - Page 48

48
Counter
output
control
The
counter
consists
of two
high-speed
4-bit binary
counters
in cascade
giving an
8-bit
output
via
buffers
to
the
databus.
Low
to
high transitions
of
the
input
(2)
result in
synchronous
changes
of
the
outputs to
the
buffers.
The
master
reset input
MR
when
at logic
'0'
resets all
outputs
regardless
of
inputs.
The
hold HLD
pulse
is a
logic
‘O'
from the
juP; logic
'1'
enables
counting
operations.
The
8-bit
output
is
routed to an
integrated circuit
D1901
containing
eight
3-state
buffers.
The
outputs
from
the
counter
are directly
routed to
the databus by
logic
'0'
on
the ECO
(OE
)
input. This
condition
requires a
RDpulse
('0')
and
a P17
and
A7
signal
applied
together.
RD
1.4.
5.3.
Analog
control
Control
inputs
The ten
function
switches
when selected,
provide a —10V
supply
to
one of
ten
independent inputs
of D1916,
D1918.
These
integrated
circuits
are two
8-channel
analog
multiplexers,
scanned by
three
address
inputs P20',
P21
',
P22' and a
chip select
pulse
P23'.
Internally, the
analog
switches
have one side
connected to a
common
output
line (pin
3)
that
is connected
via
a
diode
V901
to
P24 of the juP
(logic
'0‘
output).
The
mode switches
are also connected to
four of
the
independent inputs
of
D1919.
The
multiplexers
act
as switch
decoders.
At the start
of a
measuring
program,
the address
lines scan
the two
1-of-8
decoders
under
software
control and
detect
the
function and
any mode
conditions.
The
control
address
signals are
derived from the
fiP
part 2
outputs P20,
P21
,
P22,
R23,
clocked
via
the bistable
flip-flop circuit
D1912.
When
trigger
level is
selected,
the —10V
on pin 4
of
D1916 is
applied to
the
NAND-gate
D1918,
input 3
to
give
a logic '1'
at the
data input
(12)
of
the GATE
control
flip-flop
D1915.