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Quectel M10 Hardware Design

Quectel M10
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M10 Hardware Design
M10_HD_V3.0 - 45 -
3.8.4. UART Application
The reference design of 3.3V level match is shown as below. When the peripheral MCU/ARM
system is 3V, the divider resistor should be changed from 5.6K to 10K.
Figure 24: 3.3V level match circuit
The reference design of 5V level match is shown as below.
The construction of dotted line can
refer to the construction of solid line. Please pay attention to direction of connection. Input dotted
line of module should refer to input solid line of the module. Output dotted line of module should
refer to output solid line of the module.
MCU/ARM
/TXD
/RXD
1K
VDD_EXT
4.7k
VCC_MCU
4.7k
4.7k
4.7k
VDD_EXT
TXD
RXD
RTS
CTS
DTR
RI
/RTS
/CTS
GND
VBAT
GPIO
STATUS
MODULE
GPIO
EINT
VCC_MCU
Voltage level: 5V
Figure 25: 5V level match circuit

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Quectel M10 Specifications

General IconGeneral
BrandQuectel
ModelM10
CategoryGSM/GPRS Modules
LanguageEnglish

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