Quectel RM510Q-GL - Reference Design of Pcie

5G Module Series
RM510Q-GL Hardware Design
RM510Q-GL_Hardware_Design 43 / 88
Table 16: Pin Definition of PCIe Interface
4.3.3. Reference Design of PCIe
The following figure shows a reference circuit for the PCIe interface.
Host Module
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
BB
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
55
53
49
47
43
41
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
VCC_IO_HOST
54
52
50
Note. The voltage level VCC_IO_HOST of these three signals depend on the host side due to open drain.
R5 0Ω
R4 0Ω
C5 220 nF
C6 220 nF
C1 220 nF
C2 220 nF
R1
10k
R2
10k
R3
NM/10k
R4
10k
Figure 19: PCIe Interface Reference Circuit
Pin No.
Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AIO
PCIe reference clock (+)
100 MHz.
Require differential impedance
of 85 Ω
53
PCIE_REFCLK_M
AIO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive (+)
Require differential impedance
of 85 Ω
47
PCIE_RX_M
AI
PCIe receive (-)
43
PCIE_TX_P
AO
PCIe transmit (+)
Require differential impedance
of 85 Ω
41
PCIE_TX_M
AO
PCIe transmit (-)
50
PCIE_RST_N
DI, OD
PCIe reset.
Active LOW.
Open drain
52
PCIE_CLKREQ_N
DO, OD
PCIe clock request.
Active LOW.
Open drain
54
PCIE_WAKE_N
DO, OD
PCIe wake up.
Active LOW.
Open drain