5G Module Series
RM520N-GL_Hardware_Design 49 / 84
capacitors on your schematic and PCB.
The following principles of PCIe interface design should be complied with to meet PCIe specification.
⚫ Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
crystal, and oscillator signals.
⚫ Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫ Keep the maximum trace length less than 200 mm.
⚫ Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing
traces.
⚫ Keep the differential impedance of PCIe data trace as 85 Ω ±10 %.
⚫ You must not route PCIe data traces under components or cross them with other traces.
⚫ It is recommended to use a push-pull GPIO to output low level that approaches to 0 V rather than
using a pull-down resistor to get low level voltage. Otherwise, voltage division may be formed with
the pull-up resistor integrated inside the module, resulting in an uncertain 0 V voltage that could
furtherly lead to unpredictable problems.
Table 18: PCIe Trace Length Inside the Module
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