Rabbit 2000 - Srl (Hl)

142 Rabbit 2000/3000 Microprocessor
Description
Logically shifts to the right the bits of the data whose address is
• the data in HL, or
• the sum of the data in IX and a displacement d, or
• the sum of the data in IY and a displacement d.
Each bit is shifted to the next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the C flag. Bit 7
is reset. See figure below.
Figure 9: The bit logic of the SRL instruction.
SRL (HL)
SRL (IX+d)
SRL (IY+d)
Opcode Instruction Clocks Operation
CB 3E SRL (HL) 10* (HL) = {0,(HL)[7,1]}; CF = (HL)[0]
DD CB d 3E SRL (IX+d) 13** (IX + d) = {0,(IX + d)[7,1]};
CF = (IX + d)[0]
FD CB d 3E SRL (IY+d) 13** (IY + d) = {0,(IY + d)[7,1]};
CF = (IY + d)[0]
Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)
Flags ALTD I/O
S Z L/V C F R SP S D
• • L • • • •
7
0
CF0