Renesas RL78 - Page 32

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 32 of 85
Feb. 15, 2017
・Peripheral reset control register 0 (PRR0)
Release TAU from the reset state.
TAU0 Reset Release
Symbol: PRR0
7 6 5 4 3 2 1 0
0 IICA1RES ADCRES IICA0RES 0 SAU0RES 0 TAU0RES
x x x x x x x 0
Bit 0
TAU0RES Reset control of timer array unit 0
0 Reset control of timer array unit 0
1 Reset state of timer array unit 0.
・Peripheral reset control register 0 (PER0)
Clock su
pp
l
y
for TAU0.
Symbol: PER0
7 6 5 4 3 2 1 0
RTCWEN IICA1EN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
x x x x x x x 1
Bit 0
TAU0EN Input clock supply control for timer array unit 0
0 Stops input clock supply
1 Enables input clock supply
TAU0 Clock Su
pp
l
y