Renesas RL78 - Page 33

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 33 of 85
Feb. 15, 2017
Symbol: TPS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 PRS
031
PRS
030
0 0 PRS
021
PRS
020
PRS
013
PRS
012
PRS
011
PRS
010
PRS
003
PRS
002
PRS
001
PRS
000
x x x x x x x x 0 0 0 0 0 0 0 0
Bit 7- 0 (n = 0, 1)
PRS
0n3
PRS
0n2
PRS
0n1
PRS
0n0
Operation Clock (CK01/CK00) Selection
f
CLK
=
2MHz
f
CLK
=
5MHz
f
CLK
=
10MHz
f
CLK
=
20MHz
f
CLK
=
24MHz
0 0 0 0 f
CLK
2 MHz 5 MHz 10 MHz 20 MHz
24 MHz
0 0 0 1 f
CLK
/2 1 MHz 2.5 MHz 5 MHz 10 MHz 12 MHz
0 0 1 0 f
CLK
/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz 6 MHz
0 0 1 1 f
CLK
/2
3
250 kHz 625 kHz 1.25 MHz 2.5 MHz 3 MHz
0 1 0 0 f
CLK
/2
4
125 kHz 313 kHz 625 kHz 1.25 MHz 1.5 MHz
0 1 0 1 f
CLK
/2
5
62.5 kHz 156 kHz 313 kHz 625 kHz 750 kHz
0 1 1 0 f
CLK
/2
6
31.3 kHz 78.1 kHz 156 kHz 313 kHz 375 kHz
0 1 1 1 f
CLK
/2
7
15.6 kHz 39.1 kHz 78.1 kHz 156 kHz 187.5 kHz
1 0 0 0 f
CLK
/2
8
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 93.8 kHz
1 0 0 1 f
CLK
/2
9
3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz 46.9 kHz
1 0 1 0 f
CLK
/2
10
1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz 23.4 kHz
1 0 1 1 f
CLK
/2
11
977Hz 2.44 kHz 4.88 kHz 9.77 kHz 11.7 kHz
1 1 0 0 f
CLK
/2
12
488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
1 1 0 1 f
CLK
/2
13
244 Hz 610 Hz 1.22 kHz 2.44 kHz 2.93 kHz
1 1 1 0 f
CLK
/2
14
122 Hz 305 Hz 610 Hz 1.22 kHz 1.46 kHz
1 1 1 1 f
CLK
/2
15
61 Hz 153 Hz 305 Hz 610 Hz 732 Hz
・Timer clock selection register 0 (TPS0)
Set CK00 /
CK01 = fCLK
TAU0 Operation Clock Selection