Renesas RL78 - Page 34

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 34 of 85
Feb. 15, 2017
・Timer channel stop register 0 (TT0)
Set all TAU0 channels to operation stop state.
TAU0 All Channel Operation Stop
Symbol: TT0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 TTH
03
0 TTH
01
0 0 0 0 0 TT0
3
TT0
2
TT0
1
TT0
0
x x x x 1 x 1 x x x x x 1 1 1 1
Bit 11
TTH
03
Trigger to stop operations of higher 8-bit timer when channel 3 is in 8-bit timer mode
0 No trigger operation
1 TEHm3 bit is cleared to 0 and the count operation is stopped.
Bit 9
TTH
01
Trigger to stop operations of higher 8-bit timer when channel 1 is in 8-bit timer mode
0 No trigger operation
1 TEHm1 bit is cleared to 0 and the count operation is stopped.
Bit 3 - 0 (n = 0 - 3)
TT
0n
Trigger to stop operations for channel n
0 TEmn bit is cleared to 0 and the count operation is stopped.
1 Operations are stopped (stop trigger generated)